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24 lines
560 B
Verilog
24 lines
560 B
Verilog
`timescale 1ns / 1ps
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module address_decode(
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// Processor-side control
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input iadr_i,
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input istb_i,
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output iack_o,
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// ROM-side control
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output STB_o
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);
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// For our example, we're just going to decode address bit A12.
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// If it's high, then we assume we're accessing ROM.
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// The ROM is asynchronous, so we just tie iack_o directly to the
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// the strobe pin.
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wire rom_sel = iadr_i & istb_i;
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assign STB_o = rom_sel;
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assign iack_o = rom_sel;
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// We don't have any RAM resources to access, but if we did,
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// we would decode them here as well.
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endmodule
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