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70 lines
1.6 KiB
Verilog
70 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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module arbiter(
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// I-Port
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input [63:0] idat_i,
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input [63:0] iadr_i,
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input iwe_i,
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input icyc_i,
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input istb_i,
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input [1:0] isiz_i,
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input isigned_i,
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output iack_o,
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output [63:0] idat_o,
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// D-Port
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input [63:0] ddat_i,
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input [63:0] dadr_i,
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input dwe_i,
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input dcyc_i,
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input dstb_i,
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input [1:0] dsiz_i,
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input dsigned_i,
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output dack_o,
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output [63:0] ddat_o,
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// X-Port
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output [63:0] xdat_o,
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output [63:0] xadr_o,
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output xwe_o,
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output xcyc_o,
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output xstb_o,
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output [1:0] xsiz_o,
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output xsigned_o,
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input xack_i,
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input [63:0] xdat_i,
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// Miscellaneous
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input clk_i,
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input reset_i
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);
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reg reserve_i, reserve_d;
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wire en_i = (~reset_i & icyc_i & ~dcyc_i) |
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(~reset_i & icyc_i & dcyc_i & reserve_i & ~reserve_d);
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wire en_d = (~reset_i & ~icyc_i & dcyc_i) |
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(~reset_i & icyc_i & dcyc_i & ~reserve_i) |
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(~reset_i & icyc_i & dcyc_i & reserve_i & reserve_d);
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assign xdat_o = (en_i ? idat_i : 64'd0) | (en_d ? ddat_i : 64'd0);
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assign xadr_o = (en_i ? iadr_i : 64'd0) | (en_d ? dadr_i : 64'd0);
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assign xwe_o = (en_i & iwe_i) | (en_d & dwe_i);
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assign xcyc_o = (en_i & icyc_i) | (en_d & dcyc_i);
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assign xstb_o = (en_i & istb_i) | (en_d & dstb_i);
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assign xsiz_o = (en_i ? isiz_i : 2'd0) | (en_d ? dsiz_i : 2'd0);
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assign xsigned_o = (en_i & isigned_i) | (en_d & dsigned_i);
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assign iack_o = (en_i & xack_i);
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assign dack_o = (en_d & xack_i);
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assign idat_o = (en_i ? xdat_i : 64'd0);
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assign ddat_o = (en_d ? xdat_i : 64'd0);
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always @(posedge clk_i) begin
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reserve_i <= en_i;
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reserve_d <= en_d;
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end
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endmodule
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