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145 lines
3.9 KiB
Verilog
145 lines
3.9 KiB
Verilog
`timescale 1ns / 1ps
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module bridge(
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// FURCULA BUS
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input f_signed_i,
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input [1:0] f_siz_i,
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input [2:0] f_adr_i,
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input [63:0] f_dat_i,
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output [63:0] f_dat_o,
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// WISHBONE BUS
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output [7:0] wb_sel_o,
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output [63:0] wb_dat_o,
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input [63:0] wb_dat_i
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);
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// Wishbone SEL_O signal generation.
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wire size_byte = (f_siz_i == 2'b00);
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wire size_hword = (f_siz_i == 2'b01);
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wire size_word = (f_siz_i == 2'b10);
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wire size_dword = (f_siz_i == 2'b11);
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wire ab7 = f_adr_i[2:0] == 3'b111;
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wire ab6 = f_adr_i[2:0] == 3'b110;
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wire ab5 = f_adr_i[2:0] == 3'b101;
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wire ab4 = f_adr_i[2:0] == 3'b100;
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wire ab3 = f_adr_i[2:0] == 3'b011;
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wire ab2 = f_adr_i[2:0] == 3'b010;
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wire ab1 = f_adr_i[2:0] == 3'b001;
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wire ab0 = f_adr_i[2:0] == 3'b000;
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wire ah3 = f_adr_i[2:1] == 2'b11;
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wire ah2 = f_adr_i[2:1] == 2'b10;
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wire ah1 = f_adr_i[2:1] == 2'b01;
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wire ah0 = f_adr_i[2:1] == 2'b00;
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wire aw1 = f_adr_i[2] == 1'b1;
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wire aw0 = f_adr_i[2] == 1'b0;
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wire den = size_dword;
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wire wen1 = size_word & aw1;
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wire wen0 = size_word & aw0;
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wire hen3 = size_hword & ah3;
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wire hen2 = size_hword & ah2;
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wire hen1 = size_hword & ah1;
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wire hen0 = size_hword & ah0;
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wire ben7 = size_byte & ab7;
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wire ben6 = size_byte & ab6;
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wire ben5 = size_byte & ab5;
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wire ben4 = size_byte & ab4;
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wire ben3 = size_byte & ab3;
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wire ben2 = size_byte & ab2;
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wire ben1 = size_byte & ab1;
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wire ben0 = size_byte & ab0;
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wire sel7 = den | wen1 | hen3 | ben7;
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wire sel6 = den | wen1 | hen3 | ben6;
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wire sel5 = den | wen1 | hen2 | ben5;
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wire sel4 = den | wen1 | hen2 | ben4;
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wire sel3 = den | wen0 | hen1 | ben3;
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wire sel2 = den | wen0 | hen1 | ben2;
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wire sel1 = den | wen0 | hen0 | ben1;
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wire sel0 = den | wen0 | hen0 | ben0;
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assign wb_sel_o = {sel7, sel6, sel5, sel4, sel3, sel2, sel1, sel0};
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// Furcula-to-Wishbone Data Routing
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wire [7:0] od7 =
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(size_byte ? f_dat_i[7:0] : 0) |
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(size_hword ? f_dat_i[15:8] : 0) |
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(size_word ? f_dat_i[31:24] : 0) |
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(size_dword ? f_dat_i[63:56] : 0);
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wire [7:0] od6 =
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(size_byte ? f_dat_i[7:0] : 0) |
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(size_hword ? f_dat_i[7:0] : 0) |
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(size_word ? f_dat_i[23:16] : 0) |
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(size_dword ? f_dat_i[55:48] : 0);
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wire [7:0] od5 =
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(size_byte ? f_dat_i[7:0] : 0) |
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(size_hword ? f_dat_i[15:8] : 0) |
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(size_word ? f_dat_i[15:8] : 0) |
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(size_dword ? f_dat_i[47:40] : 0);
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wire [7:0] od4 =
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(size_byte ? f_dat_i[7:0] : 0) |
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(size_hword ? f_dat_i[7:0] : 0) |
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(size_word ? f_dat_i[7:0] : 0) |
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(size_dword ? f_dat_i[39:32] : 0);
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wire [7:0] od3 =
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(size_byte ? f_dat_i[7:0] : 0) |
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(size_hword ? f_dat_i[15:8] : 0) |
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(size_word ? f_dat_i[31:24] : 0) |
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(size_dword ? f_dat_i[31:24] : 0);
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wire [7:0] od2 =
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(size_byte ? f_dat_i[7:0] : 0) |
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(size_hword ? f_dat_i[7:0] : 0) |
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(size_word ? f_dat_i[23:16] : 0) |
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(size_dword ? f_dat_i[23:16] : 0);
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wire [7:0] od1 =
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(size_byte ? f_dat_i[7:0] : 0) |
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(size_hword ? f_dat_i[15:8] : 0) |
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(size_word ? f_dat_i[15:8] : 0) |
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(size_dword ? f_dat_i[15:8] : 0);
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wire [7:0] od0 = f_dat_i[7:0];
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assign wb_dat_o = {od7, od6, od5, od4, od3, od2, od1, od0};
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// Wishbone to Furcula Data Routing
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wire [31:0] id2 =
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(wen1 ? wb_dat_i[63:32] : 0) |
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(wen0 ? wb_dat_i[31:0] : 0);
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wire [15:0] id1 =
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(hen3 ? wb_dat_i[63:48] : 0) |
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(hen2 ? wb_dat_i[47:32] : 0) |
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(hen1 ? wb_dat_i[31:16] : 0) |
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(hen0 ? wb_dat_i[15:0] : 0);
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wire [7:0] id0 =
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(ben7 ? wb_dat_i[63:56] : 0) |
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(ben6 ? wb_dat_i[55:48] : 0) |
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(ben5 ? wb_dat_i[47:40] : 0) |
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(ben4 ? wb_dat_i[39:32] : 0) |
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(ben3 ? wb_dat_i[31:24] : 0) |
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(ben2 ? wb_dat_i[23:16] : 0) |
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(ben1 ? wb_dat_i[15:8] : 0) |
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(ben0 ? wb_dat_i[7:0] : 0);
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wire [63:32] id2s = (f_signed_i ? {32{id2[31]}} : 32'd0);
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wire [63:16] id1s = (f_signed_i ? {48{id1[15]}} : 48'd0);
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wire [63:8] id0s = (f_signed_i ? {56{id0[7]}} : 56'd0);
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assign f_dat_o =
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(size_dword ? wb_dat_i : 0) |
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(size_word ? {id2s, id2} : 0) |
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(size_hword ? {id1s, id1} : 0) |
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(size_byte ? {id0s, id0} : 0);
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endmodule
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