mirror of
https://github.com/KestrelComputer/polaris.git
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153 lines
2.3 KiB
Verilog
153 lines
2.3 KiB
Verilog
`timescale 1ns / 1ps
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module computer #(
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parameter bootrom_file = "example.hex"
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)
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(
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`ifdef VERILATOR
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input clk,
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input reset
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`endif
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);
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wire iack;
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wire [63:0] iadr;
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wire istb;
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wire [31:0] idatiL;
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wire [63:32] idatiH; // unused; just to make iverilog happy.
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wire [63:0] ddato, ddati, dadr;
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wire [1:0] dsiz;
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wire dwe, dcyc, dstb, dsigned, dack;
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wire [11:0] cadr;
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wire coe, cwe, cvalid;
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wire [63:0] cdato, cdati;
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wire STB;
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wire [63:0] romQ;
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wire [1:0] xsiz;
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wire [63:0] xadr;
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wire [63:0] xdati, xdato;
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wire xstb, xack, xsigned;
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// initial begin
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// $dumpfile("wtf.vcd"); $dumpvars;
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// end
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`ifndef VERILATOR
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reg clk, reset;
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initial begin
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clk <= 0;
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reset <= 1;
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#60; reset <= 0;
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end
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always begin
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#20 clk <= ~clk;
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end
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`endif
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PolarisCPU cpu(
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.fence_o(),
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.trap_o(),
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.cause_o(),
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.mepc_o(),
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.mpie_o(),
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.mie_o(),
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.ddat_o(ddato),
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.dadr_o(dadr),
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.dwe_o(dwe),
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.dcyc_o(dcyc),
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.dstb_o(dstb),
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.dsiz_o(dsiz),
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.dsigned_o(dsigned),
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.irq_i(1'b0),
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.iack_i(iack),
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.idat_i(idatiL),
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.iadr_o(iadr),
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.istb_o(istb),
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.dack_i(dack),
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.ddat_i(ddati),
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.cadr_o(cadr),
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.coe_o(coe),
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.cwe_o(cwe),
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.cvalid_i(cvalid),
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.cdat_o(cdato),
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.cdat_i(cdati),
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.clk_i(clk),
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.reset_i(reset)
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);
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arbiter arbiter(
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.idat_i(64'd0), // CPU cannot write via I-port.
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.iadr_i(iadr),
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.iwe_i(1'b0),
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.icyc_i(istb),
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.istb_i(istb),
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.isiz_i({istb, 1'b0}),
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.isigned_i(1'b0),
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.iack_o(iack),
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.idat_o({idatiH, idatiL}),
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.ddat_i(ddato),
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.dadr_i(dadr),
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.dwe_i(dwe),
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.dcyc_i(dcyc),
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.dstb_i(dstb),
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.dsiz_i(dsiz),
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.dsigned_i(dsigned),
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.dack_o(dack),
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.ddat_o(ddati),
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.xdat_o(xdato),
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.xadr_o(xadr),
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.xwe_o(),
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.xcyc_o(),
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.xstb_o(xstb),
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.xsiz_o(xsiz),
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.xsigned_o(xsigned),
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.xack_i(xack),
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.xdat_i(xdati),
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.clk_i(clk),
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.reset_i(reset)
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);
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bridge bridge(
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.f_signed_i(xsigned),
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.f_siz_i(xsiz),
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.f_adr_i(xadr[2:0]),
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.f_dat_i(xdato),
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.f_dat_o(xdati),
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.wb_sel_o(),
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.wb_dat_i(romQ),
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.wb_dat_o()
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);
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rom #(.bootrom_file(bootrom_file)) rom(
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.A(xadr[11:3]),
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.Q(romQ),
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.STB(STB)
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);
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address_decode ad(
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.iadr_i(xadr[12]),
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.istb_i(xstb),
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.iack_o(xack),
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.STB_o(STB)
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);
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output_csr outcsr(
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.cadr_i(cadr),
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.cvalid_o(cvalid),
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.cdat_o(cdati),
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.cdat_i(cdato),
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.coe_i(coe),
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.cwe_i(cwe),
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.clk_i(clk)
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);
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endmodule
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