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20 lines
344 B
Verilog
20 lines
344 B
Verilog
`timescale 1ns / 1ps
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module rom #(
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parameter bootrom_file = ""
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)
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(
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input [11:3] A, // Address
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output [63:0] Q, // Data output
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input STB // True if ROM is being accessed.
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);
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reg [63:0] contents[0:511];
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wire [63:0] results = contents[A];
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assign Q = STB ? results : 0;
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initial begin
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$readmemh(bootrom_file, contents);
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end
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endmodule
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