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1bd74ad3d1e8d21f86d1a6be35abfcdf27c0208a
Commit Graph

150 Commits

Author SHA1 Message Date
Martin Kroeker
6ed4cc9c86 Add WebAssembly/Emscripten as a dedicated architecute and target 2026-03-15 19:40:14 +01:00
Martin Kroeker
2346d0bdc4 Add HAVE_SME for VortexM4 only with non-gcc compilers 2025-10-19 13:32:54 -07:00
Martin Kroeker
9bfc3612f9 Merge branch 'OpenMathLib:develop' into issue5414 2025-10-12 09:18:06 -07:00
Peter Collingbourne
6f3691a84b Fix cross compilation for x86 targets from non-x86 
When building on a non-x86 host the Makefile definitions for HAVE_* are
never printed which leads to build failures and/or silently targeting the
wrong microarchitecture. The issue is that INTEL_AMD is defined if the
host architecture is x86, but for cross builds we need to test whether
the target is x86. Test for that using the macro FORCE_INTEL.
 2025-10-08 13:22:06 -07:00
Martin Kroeker
1ee8879c78 Add VORTEXM4 2025-08-20 09:59:32 -07:00
Chris Sidebottom
87247daadc Add NEOVERSEV2 target support 
Did a quick run around to make `TARGET=NEVOERSEV2` build successfully.

Fixes #5385
 2025-07-24 12:40:31 +01:00
Martin Kroeker
3d31887073 Merge pull request #5362 from Mousius/fix-bf16 
Fix SBGEMM BFLOAT16 build
 2025-07-08 14:35:50 +02:00
Chris Sidebottom
552e1c7a7a Correct compiler flags for NEOVERSEV1 target 2025-07-07 11:26:36 +00:00
pratiklp00
1dde4a13c0 p11 changes 2025-06-26 00:03:38 -05:00
davidz-ampere
aa90ab4142 Add support for Ampere AmpereOne processors 2025-06-24 00:12:34 -04:00
davidz-ampere
be68ef03b4 Add support for Ampere processors 2025-06-15 22:00:40 -04:00
Vaisakh K V
d23eb3b93e Support for SME1 based sgemm_direct kernel for cblas_sgemm level 3 API 
* Added ARMV9SME target
* Added SGEMM_DIRECT kernel based on SME1
 2025-02-13 14:51:21 +05:30
gxw
48698b2b1d LoongArch64: Rename core 
Use microarchitecture name instead of meaningless strings to name the core,
the legacy core is still retained.
1. Rename LOONGSONGENERIC to LA64_GENERIC
2. Rename LOONGSON3R5 to LA464
3. Rename LOONGSON2K1000 to LA264
 2024-09-29 09:35:21 +08:00
Martin Kroeker
b925f61fb0 Add support for Cortex-A76 2024-04-02 19:44:17 +02:00
Chip-Kerchner
bf2310442b Fix get_num_cores for AIX. 2024-02-21 13:26:28 -06:00
Sergei Lewis
1093def0d1 Merge branch 'risc-v' into develop 2024-01-29 11:11:39 +00:00
Andrey Sokolov
9c49a81d54 Resolve conflicts 2024-01-23 19:08:53 +03:00
kseniyazaytseva
e1afb23811 Fix BLAS and LAPACK tests for C910V and RISCV64_ZVL256B targets 
* Fixed bugs in dgemm, [a]min\max, asum kernels
* Added zero checks for BLAS kernels
* Added dsdot implementation for RVV 0.7.1
* Fixed bugs in _vector files for C910V and RISCV64_ZVL256B targets
* Added additional definitions for RISCV64_ZVL256B target
 2024-01-23 19:01:31 +03:00
Dirreke
ec89466e14 Add CSKY support 2024-01-16 23:45:06 +08:00
Octavian Maghiar
e4586e81b8 [RISC-V] Add RISC-V Vector 128-bit target 
Current RVV x280 target depends on vlen=512-bits for Level 3 operations.
Commit adds generic target that supports vlen=128-bits.
New target uses the same scalable kernels as x280 for Level 1&2 operations, and autogenerated kernels for Level 3 operations.
Functional correctness of Level 3 operations tested on vlen=128-bits using QEMU v8.1.1 for ctests and BLAS-Tester.
 2023-12-04 11:02:18 +00:00
Guillaume Horel
281e834566 do not pass -j flag to the MAKE variable 2023-03-31 09:25:51 -04:00
Martin Kroeker
31fd13d048 MIPS: make HAVE_MSA reflect cpu capability and NO_MSA software/env 2023-01-02 22:19:13 +01:00
Xianyi Zhang
e5313f53d5 Merge branch 'develop' of https://github.com/HellerZheng/OpenBLAS_riscv_x280 into HellerZheng-develop 2022-12-03 12:00:52 +08:00
Chris Sidebottom
fd4f52c797 Add SVE implementation for sdot/ddot 
This adds an SVE implementation to sdot/ddot when available, falling back to the previous Advanced SIMD kernel where there's no SVE implementation for the kernel.

All the targets were essentially treating `dot_thunderx2t99.c` as the Advanced SIMD implementation so I've renamed it to better fit with the feature detection.
 2022-12-01 12:07:50 +00:00
Heller Zheng
bef47917bd Initial version for riscv sifive x280 2022-11-15 00:06:25 -08:00
Martin Kroeker
bd30120ba7 Merge pull request #3720 from FlyGoat/mips64 
Make it work on general MIPS64 processors
 2022-08-19 20:24:27 +02:00
Jiaxun Yang
a50b29c540 Provide a fallback MIPS64_GENERIC target 
It is really dangerous to fallback to Loongson core on other
MIPS64 processors.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
 2022-08-12 13:13:28 +01:00
Jiaxun Yang
a03ed065e1 Wire up alpha in new build system 
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
 2022-08-11 15:08:46 +01:00
gxw
3573306a69 LoongArch64: Add core LOONGSON2K1000 and LOONGSONGENERIC 2022-07-25 16:04:56 +08:00
Martin Kroeker
14ae22bf7a Add fallback value for bogus sc_nprocessors_conf 2022-05-27 00:29:17 +02:00
Martin Kroeker
8f13ab94d2 Merge pull request #3613 from Rabenda/fix-riscv 
Fix riscv64 detect
 2022-05-04 07:22:47 +02:00
Martin Kroeker
18427f3759 Have getarch downgrade the RISCV C910V target to GENERIC if compiler lacks vector support 2022-05-03 23:29:55 +02:00
Han Gao
8123324c99 Fix riscv64 arch detect 
Signed-off-by: Han Gao <gaohan@uniontech.com>
 2022-04-27 02:29:43 +08:00
Martin Kroeker
48e421934f CortexX1 is only ArmV8 2022-03-28 17:31:26 +02:00
Martin Kroeker
09b8545fc5 Add initial support for M1 on Linux, Phytium FT2xxx series, ARM Cortex 510/710/X1/X2 2022-03-27 15:24:40 +02:00
Martin Kroeker
93a81856ae Revert AVX512 capability check from PR #1980 (moved to build) 2022-03-23 15:22:13 +01:00
Martin Kroeker
bc93f468ef Add Elbrus E2000 architecture as generic x86_64 compatible 2022-01-22 18:53:38 +01:00
Sunita Nadampalli
19c8f615dc OpenBLAS: aarch64: Add neoverse-v1/n2 architecture specifics 2022-01-07 00:28:17 +00:00
Martin Kroeker
454edd741c Merge pull request #3425 from binebrank/arm_sve_dgemm 
Add dgemm kernel for arm64 SVE
 2021-11-26 16:14:55 +01:00
Bine Brank
9388f05a3c configure SVE Makefile 2021-11-21 18:33:43 +01:00
Martin Kroeker
a569fa1540 MIPS P5600 and 24KC,1004K cpus do not support MSA 2021-11-13 23:26:48 +01:00
Bine Brank
7093372e32 add ARMV8SVE target 2021-11-01 22:53:21 +01:00
Martin Kroeker
22bf5c27ba Add basic support for the Fujitsu A64FX (#3415) 
* Add initial support for Fujitsu A64FX as generic ARMV8
 2021-10-18 15:00:19 +02:00
Wangyang Guo
4280dff103 Add NO_AVX=1 fallbacks to Sapphire Rapids build 2021-10-12 01:39:09 -07:00
Wangyang Guo
3dc6052c7e initial support for Sapphire Rapids platform 2021-10-12 01:30:40 -07:00
Martin Kroeker
32fee86033 Correct misplaced ifdef lines 2021-09-06 23:44:20 +02:00
Martin Kroeker
72f3ce5f08 Add NO_AVX=1 fallbacks to newer generation x86_64 for completeness (#3360) 
* Add NO_AVX=1 fallbacks to newer generation x86_64 for completeness

* Update .travis.yml
 2021-09-05 20:35:48 +02:00
gxw
af0a69f355 Add support for LOONGARCH64 2021-07-27 15:29:12 +08:00
User User-User
b7da75e4fd WiP CORTEX A55 support 2021-06-19 21:37:51 +02:00
Aurelien Jarno
0a535e58d8 getarch.c: define OPENBLAS_SUPPORTED for riscv64 2020-12-29 12:06:39 +00:00