OpenDB/tests/parser_test.defok

VERSION 5.8 ;
DIVIDERCHAR "|" ;
BUSBITCHARS "<>" ;
DESIGN counter ;
UNITS DISTANCE MICRONS 1000 ;
PROPERTYDEFINITIONS
DESIGN ER_routing_mode STRING "trial_opt" ;
DESIGN FE_CORE_BOX_LL_X REAL 0.42 ;
DESIGN FE_CORE_BOX_UR_X REAL 67.032 ;
DESIGN FE_CORE_BOX_LL_Y REAL 0.448 ;
DESIGN FE_CORE_BOX_UR_Y REAL 66.208 ;
DESIGN strprop STRING "aString" ;
DESIGN intprop INTEGER 1 ;
DESIGN realprop REAL 1.1 ;
DESIGN intrangeprop INTEGER RANGE 1 100 25 ;
DESIGN realrangeprop REAL RANGE 1.1 100.1 25.25 ;
NET alpha_value REAL 1 ;
NET strprop STRING ;
NET intprop INTEGER ;
NET realprop REAL ;
NET intrangeprop INTEGER RANGE 1 100 ;
NET realrangeprop REAL RANGE 1.1 100.1 ;
COMPONENT RE REAL ;
COMPONENT IN INTEGER 2 ;
COMPONENT strprop STRING ;
COMPONENT intprop INTEGER ;
COMPONENT realprop REAL ;
COMPONENT intrangeprop INTEGER RANGE 1 100 ;
COMPONENT realrangeprop REAL RANGE 1.1 100.1 ;
COMPONENTPIN PP INTEGER ;
COMPONENTPIN strprop STRING ;
COMPONENTPIN intprop INTEGER ;
COMPONENTPIN realprop REAL ;
COMPONENTPIN intrangeprop INTEGER RANGE 1 100 ;
COMPONENTPIN realrangeprop REAL RANGE 1.1 100.1 ;
ROW X STRING ;
ROW strprop STRING ;
ROW intprop INTEGER ;
ROW realprop REAL ;
ROW intrangeprop INTEGER RANGE 1 100 ;
ROW realrangeprop REAL RANGE 1.1 100.1 ;
REGION strprop STRING ;
REGION intprop INTEGER ;
REGION realprop REAL ;
REGION intrangeprop INTEGER RANGE 1 100 ;
REGION realrangeprop REAL RANGE 1.1 100.1 ;
GROUP strprop STRING ;
GROUP intprop INTEGER ;
GROUP realprop REAL ;
GROUP intrangeprop INTEGER RANGE 1 100 ;
GROUP realrangeprop REAL RANGE 1.1 100.1 ;
SPECIALNET strprop STRING ;
SPECIALNET intprop INTEGER ;
SPECIALNET realprop REAL ;
SPECIALNET intrangeprop INTEGER RANGE 1 100 ;
SPECIALNET realrangeprop REAL RANGE 1.1 100.1 ;
NONDEFAULTRULE strprop STRING ;
NONDEFAULTRULE intprop INTEGER ;
NONDEFAULTRULE realprop REAL ;
NONDEFAULTRULE intrangeprop INTEGER RANGE 1 100 ;
NONDEFAULTRULE realrangeprop REAL RANGE 1.1 100.1 ;
END PROPERTYDEFINITIONS
DIEAREA ( 100 200 ) ( 400 600 ) ;
ROW CORE_ROW_0 CoreSite 840 896 FS DO 793 BY 1 STEP 168 0 + PROPERTY X "DOG"  ;
GCELLGRID X 0 DO 100 STEP 600 ;
GCELLGRID Y 10 DO 120 STEP 400 ;
VIAS 10 ;
    - VIA1 + RECT metal2 ( 1 2 ) ( 3 4 ) + RECT via2 ( 1 2 ) ( 3 4 ) + RECT metal3 ( 1 2 ) ( 3 4 ) ;
    - VIAGEN12_0 + RECT metal1 ( -4400 -3800 ) ( 4400 3800 ) + RECT metal2 ( -4500 -3800 ) ( 4500 3800 ) + RECT via1 ( -3600 -3800 ) ( -2000 -2200 ) + RECT via1 ( -3600 2200 ) ( -2000 3800 ) + RECT via1 ( 2000 -3800 ) ( 3600 -2200 ) + RECT via1 ( 2000 2200 ) ( 3600 3800 ) ;
    - VIAGEN12_2 + RECT metal1 ( -2500 -1500 ) ( 2500 1500 ) + RECT metal2 ( -2500 -1500 ) ( 2500 1500 ) + RECT via1 ( -2360 -960 ) ( -760 640 ) + RECT via1 ( -1320 -960 ) ( 280 640 ) + RECT via1 ( 760 -960 ) ( 2360 640 ) ;
    - VIAGEN12_3 + RECT metal1 ( -1600 -1600 ) ( 1600 1600 ) + RECT metal2 ( -1600 -1600 ) ( 1600 1600 ) + RECT via1 ( -800 -800 ) ( 800 800 ) ;
    - VIAGEN12_4 + VIARULE M2_M1 + CUTSIZE 1600 1600  + LAYERS metal1 via1 metal2  + CUTSPACING 5600 6100  + ENCLOSURE 100 100 150 150  + ROWCOL 5 14  + ORIGIN 10 -10  + OFFSET 0 0 20 -20  + PATTERNNAME 2_FFE0_3_FFFF ;
    - M2_M1rct_0 + RECT via1 ( -25 -65 ) ( 25 65 ) + RECT metal1 ( -35 -95 ) ( 35 95 ) + RECT metal2 ( -65 -65 ) ( 65 65 ) ;
    - TURNM1_1 + RECT metal1 ( -100 -60 ) ( 100 60 ) ;
    - TURNM2_1 + RECT metal2 ( -100 -60 ) ( 100 60 ) ;
    - TURNM3_1 + RECT metal3 ( -100 -60 ) ( 100 60 ) ;
    - myvia1 + RECT metal1 ( 0 0 ) ( 40000 40000 ) + RECT via1 ( 0 0 ) ( 40000 40000 ) + RECT metal2 ( 0 0 ) ( 40000 40000 ) ;
END VIAS
NONDEFAULTRULES 3 ;
    - matt
      + HARDSPACING
      + LAYER metal2 WIDTH 1 SPACING 2 WIREEXTENSION 3
      + MINCUTS via1 2
    ;
    - DEFAULT
      + LAYER metal1 WIDTH 10 SPACING 2 WIREEXTENSION 1
      + LAYER metal2 WIDTH 10 SPACING 2
      + LAYER metal3 WIDTH 11 SPACING 3
      + VIA M2_M1_via
      + VIA M3_M2_via
      + VIARULE M2_M1
      + MINCUTS via1 2
    + PROPERTY strprop "aString" intprop 1 realprop 1.1 intrangeprop 25 realrangeprop 25.25     ;
    - RULE2
      + HARDSPACING
      + LAYER metal1 WIDTH 10 SPACING 2 WIREEXTENSION 1
      + LAYER metal2 WIDTH 10 SPACING 2
      + LAYER metal3 WIDTH 11 SPACING 3
      + VIA M2_M1_via
      + VIA M3_M2_via
      + VIARULE M2_M1
      + MINCUTS via1 2
    + PROPERTY strprop "aString" intprop 1 realprop 1.1 intrangeprop 25 realrangeprop 25.25     ;
END NONDEFAULTRULES
REGIONS 2 ;
    - region1 ( -500 -500 ) ( 300 100 ) ( 500 500 ) ( 1000 1000 ) + TYPE FENCE + PROPERTY strprop "aString" intprop 1 realprop 1.1 intrangeprop 25 realrangeprop 25.25  ;
    - region2 ( 4000 0 ) ( 5000 1000 ) + TYPE GUIDE ;
END REGIONS
COMPONENTS 12 ;
    - _d0_ DFFPOSX1 + PROPERTY RE 1.1 IN 2  ;
    - _d1_ DFFPOSX1 + SOURCE NETLIST ;
    - _d2_ DFFPOSX1 + FIXED ( 1 2 ) N ;
    - _d3_ DFFPOSX1 + WEIGHT 10 ;
    - _d4_ DFFPOSX1 + REGION region1 ;
    - _d5_ DFFPOSX1 ;
    - _d6_ DFFPOSX1 ;
    - _d7_ DFFPOSX1 ;
    - _d8_ DFFPOSX1 ;
    - _g0_ NOR2X1 ;
    - _g1_ NOR2X1 ;
    - _g2_ NOR2X1 ;
END COMPONENTS
PINS 13 ;
    - inp0 + NET inp0 + DIRECTION INPUT + USE SIGNAL + FIXED ( 55 60 ) N + LAYER metal1 ( -5 -10 ) ( 5 10 ) ;
    - inp1 + NET inp1 + DIRECTION INPUT + USE SIGNAL ;
    - clk + NET clk + DIRECTION INPUT + USE SIGNAL ;
    - out[8] + NET out[8] + SPECIAL + DIRECTION INPUT + USE SIGNAL ;
    - out[7] + NET out[7] + DIRECTION INPUT + SUPPLYSENSITIVITY clk + USE SIGNAL ;
    - out[6] + NET out[6] + DIRECTION INPUT + GROUNDSENSITIVITY inp0 + USE SIGNAL ;
    - out[5] + NET out[5] + DIRECTION INPUT + USE ANALOG ;
    - out[4] + NET out[4] + DIRECTION INPUT + USE SIGNAL ;
    - out[3] + NET out[3] + DIRECTION OUTPUT + USE SIGNAL ;
    - out[2] + NET out[2] + DIRECTION OUTPUT + USE SIGNAL ;
    - out[1] + NET out[1] + DIRECTION OUTPUT + USE SIGNAL ;
    - out[0] + NET out[0] + DIRECTION OUTPUT + USE SIGNAL ;
    - vdd + NET VDD + SPECIAL + DIRECTION INPUT + USE SIGNAL ;
END PINS
PINPROPERTIES 2 ;
  - PIN clk + PROPERTY PP 3  ;
  - _d0_ CLK + PROPERTY PP 1  ;
END PINPROPERTIES
BLOCKAGES 9 ;
    - LAYER metal1 + COMPONENT _d0_ + DESIGNRULEWIDTH 6 RECT ( 1 2 ) ( 3 4 ) ;
    - LAYER metal1 + COMPONENT _d0_ + DESIGNRULEWIDTH 6 RECT ( 5 6 ) ( 7 8 ) ;
    - LAYER metal2 + SLOTS + SPACING 5 RECT ( 1 2 ) ( 3 4 ) ;
    - LAYER metal2 + PUSHDOWN RECT ( 5 6 ) ( 7 8 ) ;
    - LAYER metal3 + FILLS RECT ( 0 0 ) ( 5 2 ) ;
    - LAYER metal3 + FILLS RECT ( 3 2 ) ( 5 5 ) ;
    - PLACEMENT + COMPONENT _d0_ RECT ( 1 2 ) ( 3 4 ) ;
    - PLACEMENT + PARTIAL 12.340000 + PUSHDOWN RECT ( 1 2 ) ( 3 4 ) ;
    - PLACEMENT + SOFT RECT ( 1 2 ) ( 3 4 ) ;
END BLOCKAGES
FILLS 2 ;
    - LAYER metal1 RECT ( 1 2 ) ( 3 4 ) ;
    - LAYER metal1 + MASK 2 + OPC RECT ( 1 2 ) ( 3 4 ) ;
END FILLS
SPECIALNETS 2 ;
    - VDD ( PIN vdd ) ( * vdd ) + USE POWER
      + ROUTED metal1 20 + SHAPE RING ( 0 0 ) ( 0 20 )
      NEW metal2 20 + SHAPE STRIPE ( 0 0 ) ( 20 0 ) + SOURCE TIMING ;
    - VSS ( * gnd ) + USE GROUND
      + ROUTED metal1 10 ( 5 0 ) ( 5 20 ) + SOURCE NETLIST + FIXEDBUMP + WEIGHT 99 ;
END SPECIALNETS
NETS 24 ;
    - inp0 ( PIN inp0 ) ( _g2_ A ) ( _g1_ A ) ( _g0_ A ) + USE SIGNAL ;
    - inp1 ( PIN inp1 ) ( _g2_ B ) ( _g0_ B ) ( _g1_ B ) + USE SIGNAL ;
    - clk ( PIN clk ) ( _d5_ CLK ) ( _d3_ CLK ) ( _d6_ CLK ) ( _d4_ CLK ) ( _d1_ CLK ) ( _d8_ CLK )
      ( _d0_ CLK ) ( _d2_ CLK ) ( _d7_ CLK ) + USE SIGNAL ;
    - out[8] ( PIN out[8] ) ( _d8_ Q ) + USE SIGNAL ;
    - out[7] ( PIN out[7] ) ( _d7_ Q ) + USE SIGNAL ;
    - out[6] ( PIN out[6] ) ( _d6_ Q ) + USE SIGNAL ;
    - out[5] ( PIN out[5] ) ( _d5_ Q ) + USE SIGNAL ;
    - out[4] ( PIN out[4] ) ( _d4_ Q ) + USE SIGNAL ;
    - out[3] ( PIN out[3] ) ( _d3_ Q ) + USE SIGNAL ;
    - out[2] ( PIN out[2] ) ( _d2_ Q ) + USE SIGNAL ;
    - out[1] ( PIN out[1] ) ( _d1_ Q ) + USE SIGNAL ;
    - out[0] ( PIN out[0] ) ( _d0_ Q ) + USE SIGNAL ;
    - _w0_ ( _g0_ Y ) ( _d1_ D ) ( _d0_ D ) ( _d2_ D ) + USE SIGNAL
      + ROUTED metal3 ( 1 2 ) ( 3 * ) VIA1
      NEW metal3 ( 4 5 ) ( 6 * ) ;
    - _w1_ ( _d5_ D ) ( _g1_ Y ) ( _d3_ D ) ( _d4_ D ) + USE SIGNAL ;
    - _w2_ ( _g2_ Y ) ( _d6_ D ) ( _d8_ D ) ( _d7_ D ) + USE SIGNAL ;
    - _xout0 + USE SIGNAL + NONDEFAULTRULE matt
      + ROUTED metal2 ( 0 0 ) M2_M1_via E
      NEW metal2 TAPER ( 0 0 ) ( * 10 ) ;
    - _xout1 + USE SIGNAL + FIXEDBUMP ;
    - _xout2 + USE SIGNAL ;
    - _xout3 + USE SIGNAL ;
    - _xout4 + USE SIGNAL ;
    - _xout5 + USE SIGNAL ;
    - _xout6 + USE SIGNAL ;
    - _xout7 + USE SIGNAL ;
    - _xout8 + USE SIGNAL ;
END NETS
GROUPS 1 ;
    - group1 _d0_ _g0_ + REGION region1 + PROPERTY strprop "aString" intprop 1 realprop 1.1 intrangeprop 25 realrangeprop 25.25  ;
END GROUPS
END DESIGN