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Moving, Renaming and Documenting Config. Variables (#1764)

Browse Source 
Renamed Variables:
```
CLOCK_TREE_SYNTH -> RUN_CTS
FP_PDN_RAILS_LAYER -> FP_PDN_RAIL_LAYER
FP_PDN_UPPER_LAYER, FP_PDN_LOWER_LAYER -> FP_PDN_HORIZONTAL_LAYER, FP_PDN_VERTICAL_LAYER
```
Removed from default configuration:
```
RCX_CORNER_COUNT
RCX_MAX_RESISTANCE		
RCX_COUPLING_THRESHOLD		
RCX_CC_MODEL	
RCX_CONTEXT_DEPTH
```
Added documentation:
```
FP_PDN_CFG
FP_PDN_HSPACING
FP_PDN_VSPACING
FP_TAPCELL_DIST
DFF_LIB_SYNTH
DIODE_CELL_PIN
DIODE_CELL
STD_CELL_GROUND_PINS
CARRY_SELECT_ADDER_MAP
FULL_ADDER_MAP
STD_CELL_LIBRARY_CDL
LAYERS_RC
VIAS_RC
SYNTH_DEFINES
STA_REPORT_POWER
FP_PDN_ENABLE_GLOBAL_CONNECTIONS
PL_RESIZER_TIE_SEPERATION
QUIT_ON_HOLD_VIOLATIONS
QUIT_ON_SETUP_VIOLATIONS
QUIT_ON_TIMING_VIOLATIONS
```
Moved to pdk configuration:
```
FP_PDN_VOFFSET
FP_PDN_VPITCH
FP_PDN_HOFFSET
FP_PDN_HPITCH
```
\- Remove unneeded usage of `PL_TARGET_DENSITY_CELLS`

Addresses https://github.com/The-OpenROAD-Project/OpenLane/issues/1325
This commit is contained in:
Kareem Farid
2023-04-26 10:39:25 +02:00
committed by GitHub
parent 02a096e7af
commit 6b97e2c444
17 changed files with 56 additions and 50 deletions
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26
docs/source/for_developers/pdk_structure.md
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@@ -51,6 +51,12 @@ This section defines the necessary variables for PDK configuration file. Note th
| `FP_TAPCELL_DIST` | The distance between tapcell columns. Used in floorplanning in tapcell insertion. |
| `DEFAULT_MAX_TRAN` | Defines the default maximum transition value, used in CTS & synthesis. |
| `FP_PDN_RAIL_OFFSET` | Defines the rail offset for met1 used in PDN. <br> (Example: `0`) | |
| `FP_PDN_HSPACING` | The spacing between horizontal power/ground pair <br> (Default: `1.7`) |
| `FP_PDN_VSPACING` | The spacing between vertical power/ground pair <br> (Default: `1.7`) |
| `FP_PDN_VOFFSET` | The offset of the vertical power stripes on the metal layer 5 in the power distribution network <br> (Default: `16.32`) |
| `FP_PDN_VPITCH` | The pitch of the vertical power stripes on the metal layer 4 in the power distribution network <br> (Default: `153.6`) |
| `FP_PDN_HOFFSET` | The offset of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `16.65`) |
| `FP_PDN_HPITCH` | The pitch of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `153.18`) |
| `FP_PDN_VWIDTH` | Defines the strap width for the vertical layer used in PDN. <br> (Example: `1.6`) | |
| `FP_PDN_HWIDTH` | Defines the strap width for the horizontal layer used in PDN. <br> (Example: `1.6`) | |
| `FP_PDN_CORE_RING_VWIDTH` | Defines the vertical width for the vertical layer used to create the core ring in the PDN. <br> (Example: `20`) | |
@@ -63,6 +69,7 @@ This section defines the necessary variables for PDK configuration file. Note th
| `GRT_LAYER_ADJUSTMENTS` | Layer-specific reductions in the routing capacity of the edges between the cells in the global routing graph, delimited by commas. Values range from 0 to 1. <br> (Example: `0.99,0,0,0,0,0`)
| `FP_IO_HLAYER` | The metal layer on which to place the io pins horizontally (top and bottom of the die). <br>(Example: `met3`)|
| `FP_IO_VLAYER` | The metal layer on which to place the io pins vertically (sides of the die) <br> (Example: `met2`)|
| `FP_TAPCELL_DIST` | The horizontal distance between two tapcell columns <br> (Default: `14`) |
| `RT_MIN_LAYER` | The lowest metal layer to route on. <br>(Example: `met1`)|
| `RT_MAX_LAYER` | The highest metal layer to route on. <br> (Example: `met5`)|
| `RCX_RULES_MIN` | OpenRCX rules at the minimum corner. (Optional) |
@@ -80,6 +87,7 @@ This section defines the necessary variables to configure a standard cell librar
| `LIB_SLOWEST` | Points to the lib file, corresponding to the slowest corner, for max delay calculation during STA. |
| `LIB_FASTEST` | Points to the lib file, corresponding to the fastest corner, for min delay calculation during STA. |
| `LIB_TYPICAL` | Points to the lib file for typical delay calculation during STA. |
| `DFF_LIB_SYNTH` | Points to the lib file for used for dff mapping. If not specified, `LIB_SYNTH` is used. (Optional) |
| `PLACE_SITE` | Defines the main site used by the cells. Used during floorplanning to generate the rows. |
| `PLACE_SITE_WIDTH` | Defines the main site width. Used during floorplanning to generate the rows. |
| `PLACE_SITE_HEIGHT` | Defines the main site height. Used during floorplanning to generate the rows. |
@@ -95,21 +103,29 @@ This section defines the necessary variables to configure a standard cell librar
| `SYNTH_TIELO_PORT` | Defines the tie low cell followed by the port that implements the tie high functionality. Used in synthesis. <br> (Example: `sky130_fd_sc_hd__conb_1 LO`)|
| `FILL_CELL` | Defines the fill cell. Used in fill insertion. Can use a wild card to define a class of cells. Example `sky130_fd_sc_hd__fill_*` |
| `DECAP_CELL` | Defines the decap cell used for fill insertion. Can use a wild card to define a class of cells. Example `sky130_fd_sc_hd__fill_*` |
| `DIODE_CELL_PIN` | Defines the `DIODE_CELL` pin. This is required if `DIODE_CELL` is defined |
| `DIODE_CELL` | Defines the diode cell to be used during antenna violations fix step. <br> If this is not defined then the no antenna violations fixes will be attempted |
| `GPL_CELL_PADDING` | Cell padding value (in sites) for global placement. <br> (Example: `2`) |
| `DPL_CELL_PADDING` | Defines the number of sites to pad the cells with during detailed placement. This value should not be higher than `GPL_CELL_PADDING` unless you know what you're doing. <br> (Example: `2`) |
| `CELL_PAD_EXCLUDE` | Defines the cells to exclude from padding for both detailed placement. |
| `CTS_ROOT_BUFFER` | Defines the cell inserted at the root of the clock tree. Used in CTS. |
| `CTS_CLK_BUFFER_LIST` | Defines the list of clock buffers to be used in CTS. |
| `CTS_MAX_CAP` | Defines the maximum capacitance, used in CTS. |
| `FP_PDN_UPPER_LAYER` | Defines the upper layer used in PDN. |
| `FP_PDN_LOWER_LAYER` | Defines the lower layer used in PDN. |
| `FP_PDN_RAILS_LAYER` | Defines the rail layer used in PDN. |
| `STD_CELL_GROUND_PINS` | Defines ground pins of stdcells. Used in PDN. |
| `FP_PDN_HORIZONTAL_LAYER` | Defines the upper layer used in PDN. |
| `FP_PDN_VERTICAL_LAYER` | Defines the lower layer used in PDN. |
| `FP_PDN_RAIL_LAYER` | Defines the rail layer used in PDN. |
| `FP_PDN_RAIL_WIDTH` | Defines the rail width for the rail layer used in PDN. |
| `SYNTH_LATCH_MAP` | A pointer for the file contianing the latch mapping for yosys. |
| `TRISTATE_BUFFER_MAP` | A pointer for the file containing the tri-state buffer mapping for yosys. |
| `SYNTH_LATCH_MAP` | A pointer for the file containing the latch mapping for yosys. (Optional) |
| `TRISTATE_BUFFER_MAP` | A pointer for the file containing the tri-state buffer mapping for yosys. (Optional) |
| `CARRY_SELECT_ADDER_MAP` | A pointer for the file containing the carry-select adder mapping for Yosys. (Optional) |
| `FULL_ADDER_MAP` | A pointer for the file containing the full adder mapping for Yosys. (Optional) |
| `NO_SYNTH_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells` and if it's not found, then the original liberty will be used as is. |
| `DRC_EXCLUDE_CELL_LIST` | Specifies the file that contains the don't-use-cell-list to be excluded from the liberty file during synthesis and timing optimizations. If it's not defined, this path is searched `$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/drc_exclude.cells` and if it's not found, then the original liberty will be used as is. In other words, `DRC_EXCLUDE_CELL_LIST` contain the only excluded cell list in timing optimizations. |
| `CVC_SCRIPTS_DIR` | A directory of Circuit Validity Checker (CVC) scripts for the relevant PDK. Must contain the following set of files: `cvcrc`, an initialization file, `cdl.awk`, an awk script to remove black box definitions from SPICE files, `models`, cell models, and finally `power.awk`, an awk script that adds power information to the verilog netlists. |
| `STD_CELL_LIBRARY_CDL` | A pointer for the cdl view of the SCL. |
| `LAYERS_RC` | A comma separated list specifying capacitance and resistance per layer. Variable should be provided in the following format. `<layer_name> <capacitance> <resistance>, <layer_name> ...` ([warning](../reference/configuration.md#on-comma-delimited-variables)) (Optional) |
| `VIAS_RC` | A comma separated list specifying capacitance -only- of vias. Variable should be provided in the following format. `<layer_name> <capacitance> , <layer_name> ...` ([warning](../reference/configuration.md#on-comma-delimited-variables)) (Optional) |
## Tracks Info File

14
docs/source/reference/configuration.md
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@@ -46,6 +46,7 @@ These variables are optional that can be specified in the design configuration f
| `SYNTH_AUTONAME` | Add a synthesis step to generate names for instances. This results in instance names that can be very long, but may be more useful than the internal names that are six digit numbers. <br> Enabled = 1, Disabled = 0 <br> (Default: `0`)|
| `SYNTH_BIN` | The yosys binary used in the flow. <br> (Default: `yosys`) |
| `SYNTH_CAP_LOAD` | The capacitive load on the output ports in femtofarads. <br> (Default: `33.5` ff)|
| `SYNTH_DEFINES` | Specifies verilog defines. Variable should be provided as a json/tcl list. <br> (Default: NONE) |
| `SYNTH_MAX_FANOUT` | The max load that the output ports can drive. <br> (Default: `10` cells) |
| `SYNTH_MAX_TRAN` | The max transition time (slew) from high to low or low to high on cell inputs in ns. Used in synthesis <br> (Default: Calculated at runtime as `10%` of the provided clock period, unless this exceeds a set DEFAULT_MAX_TRAN, in which case it will be used as is). |
| `SYNTH_CLOCK_UNCERTAINTY` | Specifies a value for the clock uncertainty/jitter for timing analysis. <br> (Default: `0.25`) |
@@ -72,6 +73,7 @@ These variables are optional that can be specified in the design configuration f
| Variable | Description |
|-|-|
| `STA_REPORT_POWER` | Enables reporting power in sta. <br> (Default: `1`) |
| `EXTRA_SPEFS` | Specifies min, nom, max spef files for modules(s). Variable should be provided as a json/tcl list or a space delimited tcl string. Note that a module name is provided not an instance name. A module may have multiple instances. Each module must have define 3 files, one for each corner. For example: `module1 min1 nom1 max1 module2 min2 nom2 max2`. A file can be used multiple time in case of absence of other corner files. For example: `module nom nom nom`. In this case, the nom file will be used in all corners of sta. At all times a module must specify 3 files. <br> (Default: NONE) |
| `STA_WRITE_LIB` | Controls whether a timing model is written using OpenROAD OpenSTA after static timing analysis. This is an option as it in its current state, the timing model generation (and the model itself) can be quite buggy. <br> (Default: `1`) |
@@ -87,10 +89,7 @@ These variables are optional that can be specified in the design configuration f
| `FP_IO_MODE` | Decides the mode of the random IO placement option. 0=matching mode, 1=random equidistant mode <br> (Default: `1`)|
| `FP_WELLTAP_CELL` | The name of the welltap cell during welltap insertion. |
| `FP_ENDCAP_CELL` | The name of the endcap cell during endcap insertion. |
| `FP_PDN_VOFFSET` | The offset of the vertical power stripes on the metal layer 4 in the power distribution network <br> (Default: `16.32`) |
| `FP_PDN_VPITCH` | The pitch of the vertical power stripes on the metal layer 4 in the power distribution network <br> (Default: `153.6`) |
| `FP_PDN_HOFFSET` | The offset of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `16.65`) |
| `FP_PDN_HPITCH` | The pitch of the horizontal power stripes on the metal layer 5 in the power distribution network <br> (Default: `153.18`) |
| `FP_PDN_CFG` | Points to a pdn configuration file that describes how to construct the pdn in detail. <br> (Default: `scripts/openroad/common/pdn_cfg.tcl`) |
| `FP_PDN_AUTO_ADJUST` | Decides whether or not the flow should attempt to re-adjust the power grid, in order for it to fit inside the core area of the design, if needed. <br> 1=enabled, 0 =disabled (Default: `1`) |
| `FP_PDN_SKIPTRIM` | Enables `-skip_trim` option during pdngen which skips the metal trim step, which attempts to remove metal stubs <br> 1=enabled, 0 =disabled (Default: `1`) |
| `FP_TAPCELL_DIST` | The horizontal distance between two tapcell columns <br> (Default: `14`) |
@@ -106,6 +105,7 @@ These variables are optional that can be specified in the design configuration f
| `LEFT_MARGIN_MULT` | The core margin, in multiples of site widths, from the left boundary. If `FP_SIZING` is absolute and `CORE_AREA` is set, this variable has no effect. <br> (Default: `12`) |
| `RIGHT_MARGIN_MULT` | The core margin, in multiples of site widths, from the right boundary. If `FP_SIZING` is absolute and `CORE_AREA` is set, this variable has no effect. <br> (Default: `12`) |
| `FP_PDN_CORE_RING` | Enables adding a core ring around the design. More details on the control variables in the pdk configurations documentation. 0=Disable 1=Enable. <br> (Default: `0`) |
| `FP_PDN_ENABLE_GLOBAL_CONNECTIONS` | Enables power connection to std cells. It is rare that this variable needs to be disabled <br> (Default: `1`) |
| `FP_PDN_ENABLE_RAILS` | Enables the creation of rails in the power grid. 0=Disable 1=Enable. <br> (Default: `1`) |
| `FP_PDN_ENABLE_MACROS_GRID` | Enables the connection of macros to the top level power grid. 0=Disable 1=Enable. <br> (Default: `1`) |
| `FP_PDN_MACRO_HOOKS` | Specifies explicit power connections of internal macros to the top level power grid. As a comma-delimited ([warning](#on-comma-delimited-variables)) list of macro instance names, power domain vdd and ground net names, and macro vdd and ground pin names: `<instance_name> <vdd_net> <gnd_net> <vdd_pin> <gnd_pin>` |
@@ -154,6 +154,7 @@ These variables worked initially, but they were too sky130 specific and will be
| `PL_RANDOM_GLB_PLACEMENT` | Specifies whether the placer should run random placement or not. This is useful if the design is tiny (less than 100 cells). 0 = false, 1 = true <br> (Default: `0`) |
| `PL_RANDOM_INITIAL_PLACEMENT` | Specifies whether the placer should run random placement or not followed by replace's initial placement. This is useful if the design is tiny (less than 100 cells). 0 = false, 1 = true <br> (Default: `0`) |
| `PL_ROUTABILITY_DRIVEN` | Specifies whether the placer should use routability driven placement. 0 = false, 1 = true <br> (Default: `1`) |
| `PL_RESIZER_TIE_SEPERATION` | Distance between load and an inserted tie cell in microns. <br> (Default: `0`)|
| `PL_RESIZER_DESIGN_OPTIMIZATIONS` | Specifies whether resizer design optimizations should be performed or not. 0 = false, 1 = true <br> (Default: `1`) |
| `PL_RESIZER_TIMING_OPTIMIZATIONS` | Specifies whether resizer timing optimizations should be performed or not. 0 = false, 1 = true <br> (Default: `1`) |
| `PL_RESIZER_MAX_WIRE_LENGTH` | Specifies the maximum wire length cap used by resizer to insert buffers. If set to 0, no buffers will be inserted. Value in microns. <br> (Default: `0`)|
@@ -184,7 +185,7 @@ These variables worked initially, but they were too sky130 specific and will be
|Variable|Description|
|-|-|
| `CTS_TARGET_SKEW` | The target clock skew in picoseconds. <br> (Default: `200`ps)|
| `CLOCK_TREE_SYNTH` | Enable clock tree synthesis. <br> (Default: `1`)|
| `RUN_CTS` | Enable clock tree synthesis. <br> (Default: `1`)|
| `CTS_TOLERANCE` | An integer value that represents a tradeoff of QoR and runtime. Higher values will produce smaller runtime but worse QoR <br> (Default: `100`) |
| `CTS_SINK_CLUSTERING_SIZE` | Specifies the maximum number of sinks per cluster. <br> (Default: `25`) |
| `CTS_SINK_CLUSTERING_MAX_DIAMETER` | Specifies maximum diameter (in micron) of sink cluster. <br> (Default: `50`) |
@@ -338,6 +339,9 @@ These variables worked initially, but they were too sky130 specific and will be
| `QUIT_ON_MAGIC_DRC` | Checks for DRC violations after magic DRC is executed and exits the flow if any was found. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
| `QUIT_ON_ILLEGAL_OVERLAPS` | Checks for illegal overlaps during magic extraction. In some cases, these imply existing undetected shorts in the design. It also exits the flow if any was found. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
| `QUIT_ON_LVS_ERROR` | Checks for LVS errors after netgen LVS is executed and exits the flow if any was found. 1 = Enabled, 0 = Disabled <br> (Default: `1`)|
| `QUIT_ON_HOLD_VIOLATIONS ` | Exits the flow on hold violations at the typical corner <br> (Default: `1`)|
| `QUIT_ON_SETUP_VIOLATIONS ` | Exits the flow on setup violations at the typical corner <br> (Default: `1`)|
| `QUIT_ON_TIMING_VIOLATIONS ` | Controls `QUIT_ON_HOLD_VIOLATIONS` and `QUIT_ON_SETUP_VIOLATIONS` <br> (Default: `1`)|
| `QUIT_ON_VERILATOR_WARNINGS` | Quit on warnings generated by Verilator <br> (Default: `0`)|
| `QUIT_ON_VERILATOR_ERRORS` | Quit on errors generated by Verilator <br> (Default: `1`)|

2
docs/source/usage/hardening_macros.md
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@@ -154,7 +154,7 @@ You can read more about that [here][0].
Most of the values for clock tree synthesis are (PDK,STD_CELL_LIBRARY) specific and you can read more about those [here][8].
You can disable it by setting `CLOCK_TREE_SYNTH` to `0`.
You can disable it by setting `RUN_CTS` to `0`.
If you do not want all the clock ports to be used in clock tree synthesis, then you can use set `CLOCK_NET` to specify those ports. Otherwise, `CLOCK_NET` will be defaulted to the value of `CLOCK_PORT`.