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Ameliorate Warnings, PDN Generation, and the default design (#2066)

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~ Reimplemented the default serial/parallel multiplier to be a bit less cryptic and eliminate linter warnings; and added a proper testbench
~ Reimplemented deprecated variable translation behavior to account for the situation where a deprecated variable's value does not match the default for the new value, which causes a crash
~ Slightly improved warning for designs having been black-boxed during STA
~ PDN Generation Updates
    ~ Renamed `DESIGN_IS_CORE` to `FP_PDN_MULTILAYER` with translation behavior
    ~ PDN generation will now always attempt to extend to core ring (which is inert if core rings do not exist)
    ~ Fixed bug where `FP_PDN_MULTILAYER` being set to `0` would attempt to create a core-ring on two layers anyway
~ IR drop now prints a warning if `VSRC_LOC_FILE` is not provided
- Removed deprecation behavior for `GLB_RT` variables - it's been over a year (>=6 mo as promised)
This commit is contained in:
Mohamed Gaber
2023-12-25 20:48:46 +02:00
committed by GitHub
parent 4f5ad4e166
commit dbcc8252e9
26 changed files with 304 additions and 255 deletions
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17
docs/source/reference/configuration.md
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@@ -78,7 +78,7 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
|-|-|
| `SYNTH_AUTONAME` <a id="SYNTH_AUTONAME"></a> | Add a synthesis step to generate names for instances. This results in instance names that can be very long, but may be more useful than the internal names that are six digit numbers. <br> Enabled = 1, Disabled = 0 <br> (Default: `0`)|
| `SYNTH_BIN` <a id="SYNTH_BIN"></a> | The yosys binary used in the flow. <br> (Default: `yosys`) |
| `SYNTH_DEFINES` <a id="SYNTH_DEFINES"></a> | Specifies verilog defines. Variable should be provided as a json/tcl list. <br> (Default: NONE) |
| `SYNTH_DEFINES` <a id="SYNTH_DEFINES"></a> | Specifies verilog defines. Variable should be provided as a json/tcl list. <br> (Default: None) |
| `SYNTH_CLOCK_UNCERTAINTY` <a id="SYNTH_CLOCK_UNCERTAINTY"></a> | Specifies a value for the clock uncertainty/jitter for timing analysis. <br> (Default: `0.25`) |
| `SYNTH_CLOCK_TRANSITION` <a id="SYNTH_CLOCK_TRANSITION"></a> | Specifies a value for the clock transition /slew for timing analysis. <br> (Default: `0.15`) |
| `SYNTH_TIMING_DERATE` <a id="SYNTH_TIMING_DERATE"></a> | Specifies a derating factor to multiply the path delays with. It specifies the upper and lower ranges of timing. <br> (Default: `+5%/-5%`) |
@@ -107,7 +107,7 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
| Variable | Description |
|-|-|
| `STA_REPORT_POWER` <a id="STA_REPORT_POWER"></a> | Enables reporting power in sta. <br> (Default: `1`) |
| `EXTRA_SPEFS` <a id="EXTRA_SPEFS"></a> | Specifies min, nom, max spef files for modules(s). Variable should be provided as a json/tcl list or a space delimited tcl string. Note that a module name is provided not an instance name. A module may have multiple instances. Each module must have define 3 files, one for each corner. For example: `module1 min1 nom1 max1 module2 min2 nom2 max2`. A file can be used multiple time in case of absence of other corner files. For example: `module nom nom nom`. In this case, the nom file will be used in all corners of sta. At all times a module must specify 3 files. <br> (Default: NONE) |
| `EXTRA_SPEFS` <a id="EXTRA_SPEFS"></a> | Specifies min, nom, max spef files for modules(s). Variable should be provided as a json/tcl list or a space delimited tcl string. Note that a module name is provided not an instance name. A module may have multiple instances. Each module must have define 3 files, one for each corner. For example: `module1 min1 nom1 max1 module2 min2 nom2 max2`. A file can be used multiple time in case of absence of other corner files. For example: `module nom nom nom`. In this case, the nom file will be used in all corners of sta. At all times a module must specify 3 files. <br> (Default: None) |
| `STA_WRITE_LIB` <a id="STA_WRITE_LIB"></a> | Controls whether a timing model is written using OpenROAD OpenSTA after static timing analysis. This is an option as it in its current state, the timing model generation (and the model itself) can be quite buggy. <br> (Default: `1`) |
## Floorplanning (FP)
@@ -148,19 +148,20 @@ files you may be depending on, including headers, in `VERILOG_FILES`.
| `FP_TAP_VERTICAL_HALO` <a id="FP_TAP_VERTICAL_HALO"></a> | Specify the vertical halo size around macros during tap insertion. The value provided is in microns. <br> (Default: set to the value of `FP_TAP_HORIZONTAL_HALO`) |
| `FP_PDN_HORIZONTAL_HALO` <a id="FP_PDN_HORIZONTAL_HALO"></a> | Sets the horizontal halo around the macros during power grid insertion. The value provided is in microns. <br> (Default: `10`) |
| `FP_PDN_VERTICAL_HALO` <a id="FP_PDN_VERTICAL_HALO"></a> | Sets the vertical halo around the macros during power grid insertion. The value provided is in microns. <br> (Default: set to the value of `FP_PDN_HORIZONTAL_HALO`) |
| `DESIGN_IS_CORE` <a id="DESIGN_IS_CORE"></a> | Controls the layers used in the power grid. Depending on whether the design is the core of the chip or a macro inside the core. 1=Is a Core, 0=Is a Macro <br> (Default: `1`)|
| `FP_PIN_ORDER_CFG` <a id="FP_PIN_ORDER_CFG"></a> | Points to the pin order configuration file to set the pins in specific directions (S, W, E, N). If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. `$<number>` i.e. `$1` can be used to place a virtual pin where `<number>` is the count of virtual pins. This can create separation between pins. You can also use `@min_distance=<number>` i.e. `@min_distance=0.8` to set preferred min distance between pins in a specific direction. See spm configuration file as an example.<br> (Default: NONE)|
| `FP_CONTEXT_DEF` <a id="FP_CONTEXT_DEF"></a> | Points to the parent DEF file that includes this macro/design and uses this DEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_LEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: NONE)|
| `FP_CONTEXT_LEF` <a id="FP_CONTEXT_LEF"></a> | Points to the parent LEF file that includes this macro/design and uses this LEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_DEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: NONE)|
| `FP_PDN_MULTILAYER` <a id="FP_PDN_MULTILAYER"></a> | Controls the layers used in the power grid. If set to `0` (Tcl)/`false` (JSON), only the lower, vertical layer will be used, which is useful when hardening a macro for integrating into a larger top-level design. <br> (Default: `1`)|
| `FP_PIN_ORDER_CFG` <a id="FP_PIN_ORDER_CFG"></a> | Points to the pin order configuration file to set the pins in specific directions (S, W, E, N). If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. `$<number>` i.e. `$1` can be used to place a virtual pin where `<number>` is the count of virtual pins. This can create separation between pins. You can also use `@min_distance=<number>` i.e. `@min_distance=0.8` to set preferred min distance between pins in a specific direction. See spm configuration file as an example.<br> (Default: None)|
| `FP_CONTEXT_DEF` <a id="FP_CONTEXT_DEF"></a> | Points to the parent DEF file that includes this macro/design and uses this DEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_LEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: None)|
| `FP_CONTEXT_LEF` <a id="FP_CONTEXT_LEF"></a> | Points to the parent LEF file that includes this macro/design and uses this LEF file to determine the best locations for the pins. It must be used with `FP_CONTEXT_DEF`, otherwise it's considered non-existing. If not set, then the IO pins will be placed based on one of the other methods depending on the rest of the configurations. <br> (Default: None)|
| `FP_DEF_TEMPLATE` <a id="FP_DEF_TEMPLATE"></a> | Points to the DEF file to be used as a template when running `apply_def_template`. This will be used to exctract pin names, locations, shapes -excluding power and ground pins- as well as the die area and replicate all this information in the `CURRENT_DEF`. |
| `VDD_NETS` <a id="VDD_NETS"></a> | Specifies the power nets/pins to be used when creating the power grid for the design. |
| `GND_NETS` <a id="GND_NETS"></a> | Specifies the ground nets/pins to be used when creating the power grid for the design. |
| `SYNTH_USE_PG_PINS_DEFINES` <a id="SYNTH_USE_PG_PINS_DEFINES"></a> | Specifies the power guard used in the verilog source code to specify the power and ground pins. This is used to automatically extract `VDD_NETS` and `GND_NET` variables from the verilog, with the assumption that they will be order `inout vdd1, inout gnd1, inout vdd2, inout gnd2, ...`. |
| `FP_IO_MIN_DISTANCE` <a id="FP_IO_MIN_DISTANCE"></a> | The minmimum distance between the IOs in microns. <br> (Default: `3`) |
| `FP_PADFRAME_CFG` <a id="FP_PADFRAME_CFG"></a> | A configuration file passed to padringer, a padframe generator. <br> (Default: NONE) |
| `FP_PADFRAME_CFG` <a id="FP_PADFRAME_CFG"></a> | A configuration file passed to padringer, a padframe generator. <br> (Default: None) |
| `PDN_CFG` <a id="PDN_CFG"></a> | **Deprecated: Use `FP_PDN_CFG`**: Points to a PDN configuration file that describes how to construct the PDN in detail. |
| `FP_HORIZONTAL_HALO` <a id="FP_HORIZONTAL_HALO"></a> | **Deprecated: Use `FP_PDN_HORIZONTAL_HALO`**: Sets the horizontal halo around the macros during power grid insertion. The value provided is in microns.|
| `FP_PDN_VERTICAL_HALO` <a id="FP_PDN_VERTICAL_HALO"></a> | **Deprecated: Use `FP_PDN_VERTICAL_HALO`**: Sets the vertical halo around the macros during power grid insertion. The value provided is in microns. |
| `DESIGN_IS_CORE` <a id="DESIGN_IS_CORE"></a> | **Deprecated as even macros can have a full-stack PDN if core rings are used: New variable is `FP_PDN_MULTILAYER`** Controls the layers used in the power grid. Depending on whether the design is the core of the chip or a macro inside the core. 1=Is a Core, 0=Is a Macro <br> (Default: `1`)|
| `FP_PDN_IRDROP` <a id="FP_PDN_IRDROP"></a> | **Removed: No point running it this early in the flow**: Enable calculation of power grid IR drop during PDN generation. |
### Deprecated I/O Layer variables
@@ -367,7 +368,7 @@ For more information on integrating macros and other relevant configuration vari
|Variable|Description|
|-|-|
| `RUN_IRDROP_REPORT` <a id="RUN_IRDROP_REPORT"></a> | Creates an IR Drop report using OpenROAD PSM. 1 = Enabled, 0 = Disabled. <br> (Default: `1`) |
| `VSRC_LOC_FILES` <a id="VSRC_LOC_FILES"></a> | PSM loc file for power and ground nets. Variable should be provided as a json/tcl list or a space delimited tcl string as follows: `net1 file1 net2 file2`. See [this](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/psm#commands) for more info.<br> (Default: NONE) |
| `VSRC_LOC_FILES` <a id="VSRC_LOC_FILES"></a> | Map of voltage source nets to OpenROAD PSM location files. Variable should be provided as a Tcl dict, i.e.: `net1 file1 net2 file2`. See [this](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/psm#commands) for more info. <br> (Default: None) |
## Signoff

12
docs/source/tutorials/digital_guide.md
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@@ -58,7 +58,7 @@ Modify the `config.json` to include following:
:language: json
```
`DESIGN_IS_CORE` controls the metal levels used for power routing. Set it to `false` to use only lower levels.
`FP_PDN_MULTILAYER` controls the metal levels used for power routing. Set it to `false` to use only lower levels.
`FP_PDN_CORE_RING` is set to `false` to disable a power ring around the macroblock.
@@ -136,7 +136,7 @@ Then add `VERILOG_FILES_BLACKBOX`, `EXTRA_LEFS` and `EXTRA_GDS_FILES` to the `co
"VERILOG_FILES": "dir::src/*.v",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"DESIGN_IS_CORE": true,
"FP_PDN_MULTILAYER": true,
"EXTRA_LEFS": "/openlane/designs/ci/mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
"EXTRA_GDS_FILES": "/openlane/designs/ci/mem_1r1w/runs/full_guide/results/final/gds/mem_1r1w.gds",
@@ -156,7 +156,7 @@ This is a [known issue documented here](https://github.com/The-OpenROAD-Project/
The PDN straps will be routed in opposite directions.
In locations where the two routings cross each other,
VIAs connecting the layers are added. When `DESIGN_IS_CORE` is set to `true` then higher layers (met5 in sky130) are used.
VIAs connecting the layers are added. When `FP_PDN_MULTILAYER` is set to `true` then higher layers (met5 in sky130) are used.
If it is set to `false` then VIAs will be missing and you will get LVS issues.
### Verilog files
@@ -493,7 +493,7 @@ Fanout Cap Slew Delay Time Description
### Demo: Debugging LVS issues due to PDN issues
Copy the original `regfile_2r1w` as `regfile_2r1w_design_not_core`. Change `DESIGN_IS_CORE` to `false`.
Copy the original `regfile_2r1w` as `regfile_2r1w_design_not_core`. Change `FP_PDN_MULTILAYER` to `false`.
```
{
@@ -501,7 +501,7 @@ Copy the original `regfile_2r1w` as `regfile_2r1w_design_not_core`. Change `DESI
"VERILOG_FILES": "dir::src/*.v",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"DESIGN_IS_CORE": false,
"FP_PDN_MULTILAYER": false,
"FP_ASPECT_RATIO": 2,
"EXTRA_LEFS": "/openlane/designs/ci/mem_1r1w/runs/full_guide/results/final/lef/mem_1r1w.lef",
@@ -589,7 +589,7 @@ The submacros are by default logically connected to `VPWR/VGND` power domain.
As can be seen, the PDN is missing the power straps in layer `met5`.
Therefore the layout, does not have connections to the submacro, while the net is logically connected.
This is expected as it was disabled by setting `DESIGN_IS_CORE` to `false` above.
This is expected as it was disabled by setting `FP_PDN_MULTILAYER` to `false` above.
Of course, reverting the change fixes this issue.
:::{note}

8
docs/source/usage/advanced_power_grid_control.md
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@@ -31,7 +31,7 @@ The first decision to make at the core level is the core ring. So first, you nee
<td>
```json
"DESIGN_IS_CORE": true,
"FP_PDN_MULTILAYER": true,
"FP_PDN_CORE_RING": true,
"VDD_NETS": "vccd1 vccd2 vdda1 cdda2",
"GND_NETS": "vssd1 vssd2 vssa1 vssa2",
@@ -44,7 +44,7 @@ The first decision to make at the core level is the core ring. So first, you nee
<td>
```tcl
set ::env(DESIGN_IS_CORE) 1
set ::env(FP_PDN_MULTILAYER) 1
set ::env(FP_PDN_CORE_RING) 1
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
@@ -198,7 +198,7 @@ To begin the configurations for your macro, you want to announce that the design
<td>
```json
"DESIGN_IS_CORE": false,
"FP_PDN_MULTILAYER": false,
"FP_PDN_CORE_RING": false,
"RT_MAX_LAYER": "met4"
```
@@ -208,7 +208,7 @@ To begin the configurations for your macro, you want to announce that the design
<td>
```tcl
set ::env(DESIGN_IS_CORE) 0
set ::env(FP_PDN_MULTILAYER) 0
set ::env(FP_PDN_CORE_RING) 0
set ::env(RT_MAX_LAYER) "met4"
```

4
docs/source/usage/chip_integration.md
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@@ -99,7 +99,7 @@ It should have an `stdcell` section that includes a `core_ring` on met4 and met5
<td>
```json
"DESIGN_IS_CORE": true,
"FP_PDN_MULTILAYER": true,
"FP_PDN_CORE_RING": true
```
@@ -108,7 +108,7 @@ It should have an `stdcell` section that includes a `core_ring` on met4 and met5
<td>
```tcl
set ::env(DESIGN_IS_CORE) 1
set ::env(FP_PDN_MULTILAYER) 1
set ::env(FP_PDN_CORE_RING) 1
```
</td>

4
docs/source/usage/hardening_macros.md
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@@ -21,7 +21,7 @@ Click on any variable name listed in this document to get its usage information.
* [`VERILOG_FILES`](../reference/configuration.md#VERILOG_FILES)
* [`CLOCK_PORT`](../reference/configuration.md#CLOCK_PORT)
* [`CLOCK_PERIOD`](../reference/configuration.md#CLOCK_PERIOD)
* [`DESIGN_IS_CORE`](../reference/configuration.md#DESIGN_IS_CORE) (You may leave it empty if true)
* [`FP_PDN_MULTILAYER`](../reference/configuration.md#FP_PDN_MULTILAYER) (You may leave it empty if true)
So, for example:
@@ -44,7 +44,7 @@ set ::env(DESIGN_NAME) {spm}
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
set ::env(CLOCK_PORT) {clk}
set ::env(DESIGN_IS_CORE) {0}
set ::env(FP_PDN_MULTILAYER) {0}
```
</td>