OpenLane/docs/source/flow_overview.md

OpenLane Architecture

OpenLane Flow Stages

OpenLane flow consists of several stages. By default all flow steps are run in sequence. Each stage may consist of multiple sub-stages. OpenLane can also be run interactively as shown [here][25].

1. Synthesis
   1. Yosys - Perform RTL synthesis and technology mapping.
   2. OpenSTA - Performs static timing analysis on the resulting netlist to generate timing reports
2. Floorplaning
   1. OpenROAD/Initialize Floorplan - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
   2. OpenLane IO Placer - Places the macro input and output ports
   3. OpenROAD/PDN Generator - Generates the power distribution network
   4. OpenROAD/Tapcell - Inserts welltap and endcap cells in the floorplan
3. Placement
   1. OpenROAD/RePlace - Performs global placement
   2. OpenROAD/Resizer - Performs optional optimizations on the design
   3. OpenROAD/OpenDP - Performs detailed placement to legalize the globally placed components
4. CTS
   1. OpenROAD/TritonCTS - Synthesizes the clock distribution network (the clock tree)
5. Routing
   1. OpenROAD/FastRoute - Performs global routing to generate a guide file for the detailed router
   2. OpenROAD/TritonRoute - Performs detailed routing
   3. OpenROAD/OpenRCX - Performs SPEF extraction
6. Tapeout
   1. Magic - Streams out the final GDSII layout file from the routed def
   2. KLayout - Streams out the final GDSII layout file from the routed def as a back-up
7. Signoff
   1. Magic - Performs DRC Checks & Antenna Checks
   2. Magic - Performs DRC Checks & an XOR sanity-check between the two generated GDS-II files
   3. Netgen - Performs LVS Checks

All tools in the OpenLane flow are free, libre and open-source software. While OpenLane itself as a script (and its associated build scripts) are under the Apache License, version 2.0, tools may fall under stricter licenses.

Everything in Floorplanning through Routing is done using OpenROAD and its various sub-utilities, hence the name "OpenLane."

OpenLane Output

All output run data is placed by default under ./designs/design_name/runs. Each flow cycle will output a timestamp-marked folder containing the following file structure:

<design_name>
├── config.json/config.tcl
├── runs
│   ├── <tag>
│   │   ├── config.tcl
│   │   ├── {logs, reports, tmp}
│   │   │   ├── cts
│   │   │   ├── signoff
│   │   │   ├── floorplan
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   ├── results
│   │   │   ├── final
│   │   │   ├── cts
│   │   │   ├── signoff
│   │   │   ├── floorplan
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis

To delete all generated runs under all designs: make clean_runs.