mirror of
https://github.com/The-OpenROAD-Project/OpenLane.git
synced 2026-06-10 00:12:30 +08:00
c38101ea8a
+ JSON Configs now support per-PDK and per-SCL options + JSON Configs now have a limited expression engine and a way to specify the current working directory and glob inside of it + Created script to help migrate tcl configs to json configs + `-init_design_config` rewritten, now creates an `openlane` folder inside the design's directory. New flag `-add_to_designs` restores the previous behavior + `docs/source/configuration_files.md` created with a focus on documenting how the configuration files work, including the JSON configuration files ~ Update `picorv32` design ~ Most `config.tcl`s replaced with `config.json` alternatives ~ Global configuration files now loaded in a specific order with no glob ~ Changed default values for PL_TARGET_DENSITY ~ Documentation updates to support the use of configuration JSON files as a first class citizen ~ Update author list ~ Replicate override_env after second design source ~ Move verify_mismatches to before most preparation ~ flow.tcl no longer requires `-design`, is happy to use the current working directory as a default ~ replicate.py rewritten ~ update.py not rewritten, but uses click now (and an improved --help) - Removed "flag documentation" for some python scripts, just use `--help`
120 lines
4.0 KiB
Python
120 lines
4.0 KiB
Python
#!/usr/bin/python3
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# Copyright 2022 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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import os
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import glob
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import json
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import click
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import shutil
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import pathlib
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import textwrap
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def mkdirp(path):
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return pathlib.Path(path).mkdir(parents=True, exist_ok=True)
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@click.command()
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@click.option("--add-to-designs/--dont-add-to-designs", default=False, help="")
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@click.option("-d", "--design-dir", required=True, help="")
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@click.option("-n", "--design-name", required=True, help="")
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@click.option("-c", "--config-file-name", default="config.json", help="")
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@click.argument("verilog_files", nargs=-1)
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def init_config(
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add_to_designs, design_dir, design_name, config_file_name, verilog_files
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):
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_, extension = os.path.splitext(config_file_name)
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src_dir = os.path.join(design_dir, "src")
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glob_in_config = True
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if not add_to_designs:
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glob_in_config = False
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design_dir = os.path.join(".", "openlane", design_name)
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config_path = os.path.join(design_dir, config_file_name)
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mkdirp(design_dir)
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verilog_files_resolved = []
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for file in verilog_files:
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if "*" in file:
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verilog_files_resolved += glob.glob(file)
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else:
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verilog_files_resolved.append(file)
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verilog_files_rel = [
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os.path.relpath(file, design_dir) for file in verilog_files_resolved
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]
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if extension == ".tcl":
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verilog_arg = "[glob $::env(DESIGN_DIR)/src/*.v]"
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if not glob_in_config:
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verilog_arg = " ".join(
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[os.path.join("$::env(DESIGN_DIR)", file) for file in verilog_files_rel]
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)
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verilog_arg = f'"{verilog_arg}"'
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with open(config_path, "w") as f:
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f.write(
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textwrap.dedent(
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f"""
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set ::env(DESIGN_NAME) {{{design_name}}}
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set ::env(VERILOG_FILES) {verilog_arg}
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set ::env(CLOCK_PORT) "clk"
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set ::env(CLOCK_PERIOD) "10.0"
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set ::env(DESIGN_IS_CORE) {{1}}
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set tech_specific_config "$::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl"
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if {{ [file exists $tech_specific_config] == 1 }} {{
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source $tech_specific_config
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}}
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"""
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)
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)
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elif extension == ".json":
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verilog_arg = "dir::src/*.v"
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if not glob_in_config:
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verilog_arg = " ".join(verilog_files_rel)
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with open(config_path, "w") as f:
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f.write(
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json.dumps(
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{
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"DESIGN_NAME": design_name,
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"VERILOG_FILES": verilog_arg,
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"CLOCK_PORT": "clk",
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"CLOCK_PERIOD": 10.0,
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"DESIGN_IS_CORE": True,
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},
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indent=4,
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sort_keys=False,
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)
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)
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else:
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raise Exception(f"Unsupported extension '{extension}' for configuration files.")
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if add_to_designs:
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mkdirp(src_dir)
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for src in verilog_files_resolved:
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dst = os.path.join(src_dir, os.path.basename(src))
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shutil.copyfile(src, dst, follow_symlinks=True)
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else:
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gitignore_path = os.path.join(design_dir, ".gitignore")
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with open(gitignore_path, "w") as f:
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f.write("/runs\n")
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print(config_path, end="")
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if __name__ == "__main__":
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init_config()
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