mirror of
https://github.com/The-OpenROAD-Project/OpenLane.git
synced 2026-05-29 00:23:55 +08:00
003992ec39
- Removed the `-min/-max` options from read_liberty since they shouldn't be used for modeling different process corners (https://github.com/The-OpenROAD-Project/OpenLane/issues/671). - Updated the base SDC file to include information about clock uncertainty, clock transition, and timing derate. - Updated the timing/design optimizations to be done at the typical corner. - Updated the STA script to generate the SDF file after the routing is concluded. - Updated the STA script to report more information like clock skew, worst slack, power, area. - Added some fixes to the report generation to retain the log file index so that we can easily keep track of when the reports are generated.
40 lines
2.0 KiB
Tcl
40 lines
2.0 KiB
Tcl
if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
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create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD)
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} else {
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create_clock -name __VIRTUAL_CLK__ -period $::env(CLOCK_PERIOD)
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set ::env(CLOCK_PORT) __VIRTUAL_CLK__
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}
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set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
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set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
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puts "\[INFO\]: Setting output delay to: $output_delay_value"
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puts "\[INFO\]: Setting input delay to: $input_delay_value"
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set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
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set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
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#set rst_indx [lsearch [all_inputs] [get_port resetn]]
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set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
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#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
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set all_inputs_wo_clk_rst $all_inputs_wo_clk
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# correct resetn
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set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
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#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
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set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
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# TODO set this as parameter
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set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
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set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
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puts "\[INFO\]: Setting load to: $cap_load"
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set_load $cap_load [all_outputs]
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puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks $::env(CLOCK_PORT)]
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puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks $::env(CLOCK_PORT)]
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puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
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set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
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set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] |