mirror of
https://github.com/The-OpenROAD-Project/OpenLane.git
synced 2026-05-29 00:23:55 +08:00
7a65b61b17
+ Added linting rules for flake8, formatting with black + Added a GitHub Action to enforce lint/format rules
301 lines
9.9 KiB
Python
301 lines
9.9 KiB
Python
#!/usr/bin/env python3
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# Copyright 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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import os
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import sys
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import argparse
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from subprocess import Popen, PIPE
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import odb
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parser = argparse.ArgumentParser(
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description="Add cell power connections in the netlist. Useful for LVS purposes."
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)
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parser.add_argument("--input-def", "-d", required=True, help="DEF view of the design")
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parser.add_argument(
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"--input-lef",
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"-l",
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required=True,
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help="LEF file needed to have a proper view of the design. Every cell having a pin labeled as a power pin (e.g., USE POWER) will be connected to the power/ground port of the design.",
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)
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parser.add_argument(
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"--power-port",
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"-v",
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help="Name of the power port of the design. The power pin of the subcells will be connected to it by default",
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)
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parser.add_argument(
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"--ground-port",
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"-g",
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help="Name of the ground port of the design. The ground pin of the subcells will be connected to it by default",
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)
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parser.add_argument(
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"--powered-netlist",
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"-pv",
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help="A structural verilog netlist, readable by openroad, that includes extra power connections that are to be applied after connecting to the default power-port and ground-port specified.",
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)
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parser.add_argument("--ignore-missing-pins", "-q", action="store_true", required=False)
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parser.add_argument(
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"--output", "-o", default="output.def", help="Output modified netlist"
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)
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# parser.add_argument('--create-pg-ports',
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# help='Create power and ground ports if not found')
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args = parser.parse_args()
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def_file_name = args.input_def
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lef_file_name = args.input_lef
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power_port_name = args.power_port
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ground_port_name = args.ground_port
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powered_netlist_file_name = args.powered_netlist
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ignore_missing_pins = args.ignore_missing_pins
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output_file_name = args.output
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def get_power_ground_ports(ports):
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vdd_ports = []
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gnd_ports = []
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for port in ports:
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if port.getSigType() == "POWER" or port.getName() == power_port_name:
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vdd_ports.append(port)
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elif port.getSigType() == "GROUND" or port.getName() == ground_port_name:
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gnd_ports.append(port)
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return (vdd_ports, gnd_ports)
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def find_power_ground_port(port_name, ports):
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for port in ports:
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if port.getName() == port_name:
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return port
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return None
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db = odb.dbDatabase.create()
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odb.read_lef(db, lef_file_name)
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odb.read_def(db, def_file_name)
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chip = db.getChip()
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block = chip.getBlock()
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design_name = block.getName()
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print("Top-level design name:", design_name)
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VDD_PORTS, GND_PORTS = get_power_ground_ports(block.getBTerms())
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assert (
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VDD_PORTS and GND_PORTS
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), "No power ports found at the top-level. Make sure that they exist and have the USE POWER|GROUND property or they match the arguments specified with --power-port and --ground-port."
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vdd_net_idx = None
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for index, port in enumerate(VDD_PORTS):
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if port.getNet().getName() == power_port_name:
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vdd_net_idx = index
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gnd_net_idx = None
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for index, port in enumerate(GND_PORTS):
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if port.getNet().getName() == ground_port_name:
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gnd_net_idx = index
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assert (
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vdd_net_idx is not None
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), "Can't find power net at the top-level. Make sure that argument specified with --power-port."
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assert (
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gnd_net_idx is not None
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), "Can't find ground net at the top-level. Make sure that argument specified with --ground-port."
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DEFAULT_VDD = VDD_PORTS[vdd_net_idx].getNet()
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DEFAULT_GND = GND_PORTS[gnd_net_idx].getNet()
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print("Default power net: ", DEFAULT_VDD.getName())
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print("Default ground net:", DEFAULT_GND.getName())
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print("Found a total of", len(VDD_PORTS), "power ports.")
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print("Found a total of", len(GND_PORTS), "ground ports.")
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modified_cells = 0
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cells = block.getInsts()
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for cell in cells:
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iterms = cell.getITerms()
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cell_name = cell.getName()
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if len(iterms) == 0:
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continue
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VDD_ITERMS = []
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GND_ITERMS = []
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VDD_ITERM_BY_NAME = None
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GND_ITERM_BY_NAME = None
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for iterm in iterms:
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if iterm.getSigType() == "POWER":
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VDD_ITERMS.append(iterm)
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elif iterm.getSigType() == "GROUND":
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GND_ITERMS.append(iterm)
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elif iterm.getMTerm().getName() == power_port_name:
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VDD_ITERM_BY_NAME = iterm
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elif iterm.getMTerm().getName() == ground_port_name: # note **PORT**
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GND_ITERM_BY_NAME = iterm
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if len(VDD_ITERMS) == 0:
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print(
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"Warning: No pins in the LEF view of", cell_name, " marked for use as power"
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)
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print(
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"Warning: Attempting to match power pin by name (using top-level port name) for cell:",
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cell_name,
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)
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if VDD_ITERM_BY_NAME is not None: # note **PORT**
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print("Found", power_port_name, "using that as a power pin")
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VDD_ITERMS.append(VDD_ITERM_BY_NAME)
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if len(GND_ITERMS) == 0:
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print(
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"Warning: No pins in the LEF view of",
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cell_name,
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" marked for use as ground",
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)
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print(
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"Warning: Attempting to match ground pin by name (using top-level port name) for cell:",
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cell_name,
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)
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if GND_ITERM_BY_NAME is not None: # note **PORT**
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print("Found", ground_port_name, "using that as a ground pin")
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GND_ITERMS.append(GND_ITERM_BY_NAME)
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if len(VDD_ITERMS) == 0 or len(GND_ITERMS) == 0:
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print("Warning: not all power pins found for cell:", cell_name)
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if ignore_missing_pins:
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print("Warning: ignoring", cell_name, "!!!!!!!")
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continue
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else:
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print("Exiting... Use --ignore-missing-pins to ignore such errors")
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sys.exit(1)
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if len(VDD_ITERMS) > 2:
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print("Warning: cell", cell_name, "has", len(VDD_ITERMS), "power pins.")
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if len(GND_ITERMS) > 2:
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print("Warning: cell", cell_name, "has", len(GND_ITERMS), "ground pins.")
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for VDD_ITERM in VDD_ITERMS:
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if VDD_ITERM.isConnected():
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pin_name = VDD_ITERM.getMTerm().getName()
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cell_name = cell_name
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print(
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"Warning: power pin", pin_name, "of", cell_name, "is already connected"
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)
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print("Warning: ignoring", cell_name + "/" + pin_name, "!!!!!!!")
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else:
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VDD_ITERM.connect(DEFAULT_VDD)
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for GND_ITERM in GND_ITERMS:
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if GND_ITERM.isConnected():
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pin_name = GND_ITERM.getMTerm().getName()
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cell_name = cell_name
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print(
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"Warning: ground pin", pin_name, "of", cell_name, "is already connected"
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)
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print("Warning: ignoring", cell_name + "/" + pin_name, "!!!!!!!")
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else:
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GND_ITERM.connect(DEFAULT_GND)
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modified_cells += 1
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print(
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"Modified power connections of",
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modified_cells,
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"cells (Remaining:",
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len(cells) - modified_cells,
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").",
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)
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# apply extra special connections taken from another netlist:
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if powered_netlist_file_name is not None and os.path.exists(powered_netlist_file_name):
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tmp_def_file = f"{os.path.splitext(powered_netlist_file_name)[0]}.def"
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openroad_script = []
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openroad_script.append(f"read_lef {lef_file_name}")
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openroad_script.append(f"read_verilog {powered_netlist_file_name}")
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openroad_script.append(f"link_design {design_name}")
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openroad_script.append(f"write_def {tmp_def_file}")
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openroad_script.append("exit")
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p = Popen(["openroad"], stdout=PIPE, stdin=PIPE, stderr=PIPE, encoding="utf8")
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openroad_script = "\n".join(openroad_script)
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output = p.communicate(openroad_script)
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print("STDOUT:")
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print(output[0].strip())
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print("STDERR:")
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print(output[1].strip())
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print("openroad exit code:", p.returncode)
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assert p.returncode == 0, p.returncode
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assert os.path.exists(tmp_def_file), "DEF file doesn't exist"
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db_power = odb.dbDatabase.create()
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odb.read_lef(db_power, lef_file_name)
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odb.read_def(db_power, tmp_def_file)
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chip_power = db_power.getChip()
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block_power = chip_power.getBlock()
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assert block_power.getName() == design_name
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print("Successfully created a new database")
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POWER_GROUND_PORT_NAMES = [port.getName() for port in VDD_PORTS + GND_PORTS]
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# using get_power_ground_ports doesn't work since the pins weren't
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# created using pdngen
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power_ground_ports = [
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port
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for port in block_power.getBTerms()
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if port.getName() in POWER_GROUND_PORT_NAMES
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]
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for port in power_ground_ports:
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iterms = port.getNet().getITerms()
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for iterm in iterms:
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inst_name = iterm.getInst().getName()
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pin_name = iterm.getMTerm().getName()
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original_inst = block.findInst(inst_name)
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assert original_inst is not None, (
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"Instance "
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+ inst_name
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+ " not found in the original netlist. Perhaps it was optimized out during synthesis?"
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)
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original_iterm = original_inst.findITerm(pin_name)
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assert original_iterm is not None, (
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inst_name + " doesn't have a pin named " + pin_name
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)
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original_port = find_power_ground_port(
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port.getName(), VDD_PORTS + GND_PORTS
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)
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assert original_port is not None, (
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port.getName() + " not found in the original netlist."
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)
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original_iterm.connect(original_port.getNet())
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print("Modified connections between", port.getName(), "and", inst_name)
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odb.write_def(block, output_file_name)
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