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43 lines
1.3 KiB
Modula-2
43 lines
1.3 KiB
Modula-2
# reg1 1 clock pin, placed
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VERSION 5.8 ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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DESIGN reg1 ;
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UNITS DISTANCE MICRONS 100 ;
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DIEAREA ( 0 0 ) ( 40000 40000 ) ;
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COMPONENTS 5 ;
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- r1 DFF_X1 + PLACED ( 10000 20000 ) N ;
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- r2 DFF_X1 + PLACED ( 20000 10000 ) N ;
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- r3 DFF_X1 + PLACED ( 30000 30000 ) N ;
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- u1 BUF_X1 + PLACED ( 40000 10000 ) N ;
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- u2 AND2_X1 + PLACED ( 10000 40000 ) N ;
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END COMPONENTS
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PINS 3 ;
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- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL + FIXED ( 0 0 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
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- in2 + NET in2 + DIRECTION INPUT + USE SIGNAL + FIXED ( 0 0 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
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- clk + NET clk + DIRECTION INPUT + USE SIGNAL + FIXED ( 10000 3333 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
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- out + NET out + DIRECTION OUTPUT + USE SIGNAL + FIXED ( 3333 10000 ) N + LAYER metal1 ( 0 0 ) ( 0 0 ) ;
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END PINS
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SPECIALNETS 2 ;
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- VSS ( * VSS )
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+ USE GROUND ;
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- VDD ( * VDD )
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+ USE POWER ;
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END SPECIALNETS
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NETS 10 ;
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- in1 ( PIN in1 ) ( r1 D ) + USE SIGNAL ;
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- in2 ( PIN in2 ) ( r2 D ) + USE SIGNAL ;
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- clk ( PIN clk ) ( r1 CK ) ( r2 CK ) ( r3 CK ) + USE SIGNAL ;
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- r1q ( r1 Q ) ( u2 A1 ) + USE SIGNAL ;
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- r2q ( r2 Q ) ( u1 A ) + USE SIGNAL ;
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- u1z ( u2 A2 ) ( u1 Z ) + USE SIGNAL ;
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- u2z ( u2 ZN ) ( r3 D ) + USE SIGNAL ;
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- out ( r3 Q ) ( PIN out ) + USE SIGNAL ;
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END NETS
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END DESIGN
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