Merge pull request #300 from The-OpenROAD-Project-staging/secure-sta-test-suite
Some checks failed
Automatically sync branch from upstream. / Automatic sync 'master' from The-OpenROAD-Project/OpenSTA (push) Has been cancelled
Lint Bazel / Run buildifier format (push) Has been cancelled
Lint Bazel / Run buildifier lint (push) Has been cancelled
CI / build (push) Has been cancelled
Scan Code with pre commit trigger / Security-Scan (push) Has been cancelled

test: Add test infrastructure and sample test cases
This commit is contained in:
Vitor Bandeira
2026-03-18 08:54:06 -03:00
committed by GitHub
167 changed files with 2628170 additions and 41 deletions

View File

@@ -0,0 +1,6 @@
sta_module_tests("network"
TESTS
query
)
add_subdirectory(cpp)

View File

@@ -0,0 +1,16 @@
add_executable(TestNetwork TestNetwork.cc)
target_link_libraries(TestNetwork
OpenSTA
GTest::gtest
GTest::gtest_main
${TCL_LIBRARY}
)
target_include_directories(TestNetwork PRIVATE
${STA_HOME}/include/sta
${STA_HOME}
${CMAKE_BINARY_DIR}/include/sta
)
gtest_discover_tests(TestNetwork
WORKING_DIRECTORY ${STA_HOME}
PROPERTIES LABELS "cpp\;module_network"
)

File diff suppressed because it is too large Load Diff

View File

@@ -0,0 +1,3 @@
Cells: 3
Nets: 6
Ports: 4

View File

@@ -0,0 +1,35 @@
# Read design and query network objects
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog network_test1.v
link_design network_test1
# Query cells
set cells [get_cells *]
puts "Cells: [llength $cells]"
if { [llength $cells] != 3 } {
puts "FAIL: expected 3 cells"
exit 1
}
# Query nets
set nets [get_nets *]
puts "Nets: [llength $nets]"
if { [llength $nets] == 0 } {
puts "FAIL: no nets found"
exit 1
}
# Query pins
set pins [get_pins buf1/*]
if { [llength $pins] == 0 } {
puts "FAIL: no pins found on buf1"
exit 1
}
# Query ports
set ports [get_ports *]
puts "Ports: [llength $ports]"
if { [llength $ports] != 4 } {
puts "FAIL: expected 4 ports"
exit 1
}

View File

@@ -0,0 +1,9 @@
module network_test1 (clk, in1, in2, out1);
input clk, in1, in2;
output out1;
wire n1, n2;
BUF_X1 buf1 (.A(in1), .Z(n1));
AND2_X1 and1 (.A1(n1), .A2(in2), .ZN(n2));
DFF_X1 reg1 (.D(n2), .CK(clk), .Q(out1));
endmodule

1
network/test/regression Symbolic link
View File

@@ -0,0 +1 @@
../../test/regression

1
network/test/save_ok Symbolic link
View File

@@ -0,0 +1 @@
../../test/shared/save_ok