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test: Apply review feedback - part4
Remove unnecessary catch blocks in network, parasitics, sdc, spice, and util test modules. Add report_checks after set_wire_load_model in parasitics_wireload.tcl to verify timing changes per wireload. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
Jaehyun Kim
@@ -39,8 +39,8 @@ Path Type: max
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--- pi model very small ---
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set_pi_model u1/Y tiny: invalid command name "set_pi_model"
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set_elmore u1/Y->u2/A tiny: invalid command name "set_elmore"
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set_pi_model u1/Y tiny: done
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set_elmore u1/Y->u2/A tiny: done
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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@@ -71,12 +71,12 @@ Path Type: max
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--- pi model medium ---
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set_pi_model u2/Y medium: invalid command name "set_pi_model"
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set_elmore u2/Y->r3/D: invalid command name "set_elmore"
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set_pi_model r1/Q large: invalid command name "set_pi_model"
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set_elmore r1/Q->u1/A: invalid command name "set_elmore"
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set_pi_model r2/Q: invalid command name "set_pi_model"
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set_elmore r2/Q->u2/B: invalid command name "set_elmore"
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set_pi_model u2/Y medium: done
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set_elmore u2/Y->r3/D: done
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set_pi_model r1/Q large: done
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set_elmore r1/Q->u1/A: done
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set_pi_model r2/Q: done
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set_elmore r2/Q->u2/B: done
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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@@ -253,23 +253,23 @@ Path Type: max
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (propagated)
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0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
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11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
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14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
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0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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75.04 data arrival time
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47.84 47.84 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
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10.64 58.48 ^ u1/Y (BUFx2_ASAP7_75t_R)
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13.12 71.60 ^ u2/Y (AND2x2_ASAP7_75t_R)
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0.01 71.61 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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71.61 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (propagated)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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-5.78 494.22 library setup time
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494.22 data required time
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-5.56 494.44 library setup time
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494.44 data required time
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---------------------------------------------------------
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494.22 data required time
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-75.04 data arrival time
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494.44 data required time
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-71.61 data arrival time
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---------------------------------------------------------
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419.17 slack (MET)
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422.83 slack (MET)
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--- dmp_ceff_two_pole with pi models ---
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@@ -496,8 +496,8 @@ Slew = 4.92
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lumped dcalc u1: done
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--- override pi model ---
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re-set u1/Y: invalid command name "set_pi_model"
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re-set u2/Y: invalid command name "set_pi_model"
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re-set u1/Y: done
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re-set u2/Y: done
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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@@ -585,8 +585,8 @@ Unannotated Arcs
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internal net u2/Y -> r3/D
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annotated -report_unannotated: done
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--- SPEF override ---
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Startpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out (output port clocked by clk)
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Path Group: clk
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Path Type: max
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@@ -594,24 +594,21 @@ Path Type: max
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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12.11 12.11 clock network delay (propagated)
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0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
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49.30 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
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61.03 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
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15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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201.72 data arrival time
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0.00 12.11 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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63.46 75.57 ^ r3/Q (DFFHQx4_ASAP7_75t_R)
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13.15 88.72 ^ out (out)
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88.72 data arrival time
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500.00 500.00 clock clk (rise edge)
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11.92 511.92 clock network delay (propagated)
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0.00 511.92 clock reconvergence pessimism
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511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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-8.46 503.46 library setup time
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503.46 data required time
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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-1.00 499.00 output external delay
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499.00 data required time
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---------------------------------------------------------
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503.46 data required time
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-201.72 data arrival time
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499.00 data required time
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-88.72 data arrival time
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---------------------------------------------------------
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301.74 slack (MET)
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410.28 slack (MET)
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Found 0 unannotated drivers.
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@@ -619,8 +616,8 @@ Found 0 partially unannotated drivers.
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--- report_net ---
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Net r1q
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Pin capacitance: 0.3994-0.5226
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Wire capacitance: 13.4000-13.4000
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Total capacitance: 13.7994-13.9226
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Wire capacitance: 0.0000
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Total capacitance: 0.3994-0.5226
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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@@ -634,8 +631,8 @@ Load pins
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report_net r1q: done
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Net r2q
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Pin capacitance: 0.4414-0.5770
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Wire capacitance: 13.4000-13.4000
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Total capacitance: 13.8414-13.9770
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Wire capacitance: 0.0000
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Total capacitance: 0.4414-0.5770
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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@@ -649,8 +646,8 @@ Load pins
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report_net r2q: done
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Net u1z
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Pin capacitance: 0.3171-0.5657
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Wire capacitance: 13.4000-13.4000
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Total capacitance: 13.7171-13.9657
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Wire capacitance: 0.0000
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Total capacitance: 0.3171-0.5657
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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@@ -664,8 +661,8 @@ Load pins
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report_net u1z: done
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Net u2z
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Pin capacitance: 0.5479-0.6212
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Wire capacitance: 13.4000-13.4000
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Total capacitance: 13.9479-14.0212
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Wire capacitance: 0.0000
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Total capacitance: 0.5479-0.6212
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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@@ -28,11 +28,11 @@ report_checks
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# Set pi model with very small values
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#---------------------------------------------------------------
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puts "--- pi model very small ---"
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catch {set_pi_model u1/Y 0.00001 0.01 0.000005} msg
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puts "set_pi_model u1/Y tiny: $msg"
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sta::set_pi_model u1/Y 0.00001 0.01 0.000005
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puts "set_pi_model u1/Y tiny: done"
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catch {set_elmore u1/Y u2/A 0.00001} msg
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puts "set_elmore u1/Y->u2/A tiny: $msg"
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sta::set_elmore u1/Y u2/A 0.00001
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puts "set_elmore u1/Y->u2/A tiny: done"
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report_checks
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@@ -40,23 +40,23 @@ report_checks
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# Set pi model with medium values on multiple nets
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#---------------------------------------------------------------
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puts "--- pi model medium ---"
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catch {set_pi_model u2/Y 0.01 20.0 0.005} msg
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puts "set_pi_model u2/Y medium: $msg"
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sta::set_pi_model u2/Y 0.01 20.0 0.005
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puts "set_pi_model u2/Y medium: done"
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catch {set_elmore u2/Y r3/D 0.01} msg
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puts "set_elmore u2/Y->r3/D: $msg"
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sta::set_elmore u2/Y r3/D 0.01
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puts "set_elmore u2/Y->r3/D: done"
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catch {set_pi_model r1/Q 0.05 50.0 0.02} msg
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puts "set_pi_model r1/Q large: $msg"
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sta::set_pi_model r1/Q 0.05 50.0 0.02
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puts "set_pi_model r1/Q large: done"
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catch {set_elmore r1/Q u1/A 0.05} msg
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puts "set_elmore r1/Q->u1/A: $msg"
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sta::set_elmore r1/Q u1/A 0.05
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puts "set_elmore r1/Q->u1/A: done"
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catch {set_pi_model r2/Q 0.03 30.0 0.01} msg
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puts "set_pi_model r2/Q: $msg"
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sta::set_pi_model r2/Q 0.03 30.0 0.01
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puts "set_pi_model r2/Q: done"
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catch {set_elmore r2/Q u2/B 0.02} msg
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puts "set_elmore r2/Q->u2/B: $msg"
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sta::set_elmore r2/Q u2/B 0.02
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puts "set_elmore r2/Q->u2/B: done"
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report_checks
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@@ -99,11 +99,11 @@ puts "lumped dcalc u1: done"
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#---------------------------------------------------------------
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puts "--- override pi model ---"
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set_delay_calculator dmp_ceff_elmore
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catch {set_pi_model u1/Y 0.02 25.0 0.01} msg
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puts "re-set u1/Y: $msg"
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sta::set_pi_model u1/Y 0.02 25.0 0.01
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puts "re-set u1/Y: done"
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catch {set_pi_model u2/Y 0.005 10.0 0.002} msg
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puts "re-set u2/Y: $msg"
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sta::set_pi_model u2/Y 0.005 10.0 0.002
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puts "re-set u2/Y: done"
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report_checks
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