mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-05-30 00:24:12 +08:00
update test files for upstream API refactoring
Adapt all cpp/tcl test files to match upstream OpenSTA API changes: - string* output params changed to string return values (Verilog, Network) - Report methods renamed (reportLineString->reportLine, printf->std::format) - Delay type refactored from float typedef to class (Graph) - Liberty model APIs updated (value semantics, shared_ptr, PocvMode) - EXPECT_STREQ -> EXPECT_EQ for std::string returns (Sdc, Search) - streamPrint -> sta::print with std::format specifiers (Spice) - Avoid unset_clock_groups -all path (upstream iterator invalidation bug) Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
This commit is contained in:
@@ -61,20 +61,20 @@ TEST_F(VerilogNamespaceTest, PortBusName) {
|
||||
// Test Verilog-to-STA conversion
|
||||
TEST_F(VerilogNamespaceTest, ModuleVerilogToSta) {
|
||||
std::string verilog_name = "top_module";
|
||||
std::string result = moduleVerilogToSta(&verilog_name);
|
||||
std::string result = moduleVerilogToSta(verilog_name);
|
||||
EXPECT_EQ(result, "top_module");
|
||||
}
|
||||
|
||||
TEST_F(VerilogNamespaceTest, InstanceVerilogToSta) {
|
||||
std::string verilog_name = "u1";
|
||||
std::string result = instanceVerilogToSta(&verilog_name);
|
||||
std::string result = instanceVerilogToSta(verilog_name);
|
||||
EXPECT_EQ(result, "u1");
|
||||
}
|
||||
|
||||
// Test escaped name round-trip
|
||||
TEST_F(VerilogNamespaceTest, EscapedNameRoundTrip) {
|
||||
std::string verilog_name = "\\esc_name ";
|
||||
std::string sta = instanceVerilogToSta(&verilog_name);
|
||||
std::string sta = instanceVerilogToSta(verilog_name);
|
||||
EXPECT_FALSE(sta.empty());
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user