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Bias pin handling (#409)

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* Update STA to exclude bias pins from timing graph and subsequently in write_verilog

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* unnecessary space in orig verilog

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* Update to use well supplies rather than bias pins

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

---------

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
This commit is contained in:
Deepashree Sengupta
2026-04-07 14:00:01 -04:00
committed by GitHub
parent 645f2669c9
commit c887b2e4b3
9 changed files with 80 additions and 4 deletions
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5
include/sta/PortDirection.hh
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@@ -41,6 +41,7 @@ public:
static PortDirection *internal() { return internal_; }
static PortDirection *ground() { return ground_; }
static PortDirection *power() { return power_; }
static PortDirection *well() { return well_; }
static PortDirection *unknown() { return unknown_; }
static PortDirection *find(const char *dir_name);
std::string_view name() const { return name_; }
@@ -57,7 +58,8 @@ public:
bool isAnyTristate() const;
bool isGround() const { return this == ground_; }
bool isPower() const { return this == power_; }
// Ground or power.
bool isWell() const { return this == well_; }
// Ground, power, or well.
bool isPowerGround() const;
bool isInternal() const { return this == internal_; }
bool isUnknown() const { return this == unknown_; }
@@ -76,6 +78,7 @@ private:
static PortDirection *internal_;
static PortDirection *ground_;
static PortDirection *power_;
static PortDirection *well_;
static PortDirection *unknown_;
};