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Bias pin handling (#409)

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* Update STA to exclude bias pins from timing graph and subsequently in write_verilog

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* unnecessary space in orig verilog

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* Update to use well supplies rather than bias pins

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

---------

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
This commit is contained in:
Deepashree Sengupta
2026-04-07 14:00:01 -04:00
committed by GitHub
parent 645f2669c9
commit c887b2e4b3
9 changed files with 80 additions and 4 deletions
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11
network/PortDirection.cc
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@@ -35,6 +35,7 @@ PortDirection *PortDirection::bidirect_;
PortDirection *PortDirection::internal_;
PortDirection *PortDirection::ground_;
PortDirection *PortDirection::power_;
PortDirection *PortDirection::well_;
PortDirection *PortDirection::unknown_;
void
@@ -47,7 +48,8 @@ PortDirection::init()
internal_ = new PortDirection("internal", 4);
ground_ = new PortDirection("ground", 5);
power_ = new PortDirection("power", 6);
unknown_ = new PortDirection("unknown", 7);
well_ = new PortDirection("well", 7);
unknown_ = new PortDirection("unknown", 8);
}
void
@@ -67,6 +69,8 @@ PortDirection::destroy()
ground_ = nullptr;
delete power_;
power_ = nullptr;
delete well_;
well_ = nullptr;
delete unknown_;
unknown_ = nullptr;
}
@@ -95,6 +99,8 @@ PortDirection::find(const char *dir_name)
return ground_;
else if (stringEqual(dir_name, "power"))
return power_;
else if (stringEqual(dir_name, "well"))
return well_;
else
return nullptr;
}
@@ -125,7 +131,8 @@ bool
PortDirection::isPowerGround() const
{
return this == ground_
|| this == power_;
|| this == power_
|| this == well_;
}
} // namespace