Merge origin/master into secure-sta-test-suite

Resolve add/add conflict in test/helpers.tcl by merging both versions:
- Keep master's report_file, report_file_filter, sort_objects functions
- Keep branch's diff_files, diff_files_sorted functions
- Use master's result_dir setup with branch's mkdir logic in make_result_file

Resolve content conflict in test/regression by keeping branch's
bash/ctest launcher over master's Tcl regression script.

Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

test/get_is_memory.tcl

@@ -1,4 +1,4 @@
-# Tests whether the is_memory attribute works for cells and libcells
+# Tests whether the is_memory attribute works for instances and cells
 read_liberty gf180mcu_sram.lib.gz
 read_liberty asap7_small.lib.gz
 read_verilog get_is_memory.v

test/helpers.tcl

@@ -1,7 +1,35 @@
-# Shared test helpers for module Tcl tests.
-# Modeled after OpenROAD/test/helpers.tcl.
-# CWD is set to CMAKE_CURRENT_SOURCE_DIR by ctest.
-set result_dir [file join [pwd] "results"]
+# Helper functions common to multiple regressions.
+
+set test_dir [file dirname [file normalize [info script]]]
+set result_dir [file join $test_dir "results"]
+
+# puts [exec cat $file] without forking.
+proc report_file { file } {
+  set stream [open $file r]
+  if { [file extension $file] == ".gz" } {
+    zlib push gunzip $stream
+  }
+  gets $stream line
+  while { ![eof $stream] } {
+    puts $line
+    gets $stream line
+  }
+  close $stream
+}
+
+proc report_file_filter { file filter } {
+  set stream [open $file r]
+  gets $stream line
+  while { ![eof $stream] } {
+    set index [string first $filter $line]
+    if { $index != -1 } {
+      set line [string replace $line $index [expr $index + [string length $filter] - 1]]
+    }
+    puts $line
+    gets $stream line
+  }
+  close $stream
+}
 
 proc make_result_file { filename } {
   global result_dir
@@ -11,6 +39,10 @@ proc make_result_file { filename } {
   return [file join $result_dir $filename]
 }
 
+proc sort_objects { objects } {
+  return [sta::sort_by_full_name $objects]
+}
+
 proc diff_files_sorted { file1 file2 } {
   set stream1 [open $file1 r]
   set stream2 [open $file2 r]

test/liberty_arcs_one2one_1.ok

@@ -1,3 +1,4 @@
+Warning 1195: liberty_arcs_one2one_1.lib line 45, port Y function size does not match port size.
 Warning 1216: liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes.
 report_edges -from partial_wide_inv_cell/A[0]
 A[0] -> Y[0] combinational

test/liberty_arcs_one2one_2.ok

@@ -1,3 +1,4 @@
+Warning 1195: liberty_arcs_one2one_2.lib line 45, port Y function size does not match port size.
 Warning 1216: liberty_arcs_one2one_2.lib line 48, timing port A and related port Y are different sizes.
 report_edges -to partial_wide_inv_cell/Y[0]
 A[0] -> Y[0] combinational

test/verilog_write_escape.tcl

@@ -1,14 +1,10 @@
 # Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog
+source helpers.tcl
 read_liberty gf180mcu_sram.lib.gz
 read_liberty asap7_small.lib.gz
 read_verilog verilog_write_escape.v
 link_design multi_sink
-set output_file "verilog_write_escape_out.v"
-write_verilog $output_file
-set fp [open $output_file r]
-while {[gets $fp line] >= 0} {
-    puts $line
-}
-close $fp
-read_verilog $output_file
-file delete $output_file
+set verilog_file [make_result_file "verilog_write_escape.v"]
+write_verilog $verilog_file
+report_file $verilog_file
+read_verilog $verilog_file

test/verilog_write_escape.v

@@ -1,10 +1,10 @@
-module \multi_sink (clk);
+module multi_sink (clk);
  input clk;
  wire \alu_adder_result_ex[0] ;
  \hier_block \h1\x (.childclk(clk),  .\Y[2:1] ({ \alu_adder_result_ex[0] , \alu_adder_result_ex[0]  }) );
 endmodule // multi_sink
 
-module \hier_block (childclk, \Y[2:1] );
+module hier_block (childclk, \Y[2:1] );
    input childclk; 
    output [1:0] \Y[2:1] ;
    wire [1:0] \Y[2:1] ;