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Write verilog escape (#394)

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* Fir for write_verilog issue 3826

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* staToVerilog2 remove escaped_name+=ch

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* updated regression to remove \ from module name

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* Using helpers.tcl function to redirect results

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* add std::string and remove trailing space, update regression name

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* update regression to reflect correct output verilog name

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

---------

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
This commit is contained in:
Deepashree Sengupta
2026-03-03 00:48:15 +00:00
committed by GitHub
parent 73e1a392c5
commit eb0446d4e2
6 changed files with 46 additions and 9 deletions
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10
network/VerilogNamespace.cc
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@@ -86,15 +86,12 @@ staToVerilog(const char *sta_name)
for (const char *s = sta_name; *s ; s++) {
char ch = s[0];
if (ch == verilog_escape) {
escaped = true;
char next_ch = s[1];
if (next_ch == verilog_escape) {
escaped_name += ch;
escaped_name += next_ch;
s++;
}
else
// Skip escape.
escaped = true;
}
else {
if ((!(isalnum(ch) || ch == '_')))
@@ -124,15 +121,12 @@ staToVerilog2(const char *sta_name)
for (const char *s = sta_name; *s ; s++) {
char ch = s[0];
if (ch == verilog_escape) {
escaped = true;
char next_ch = s[1];
if (next_ch == verilog_escape) {
escaped_name += ch;
escaped_name += next_ch;
s++;
}
else
// Skip escape.
escaped = true;
}
else {
bool is_brkt = (ch == bus_brkt_left || ch == bus_brkt_right);