23 Commits

Author	SHA1	Message	Date
James Cherry	6d95ef44e5	SdcNetwork::location(pin)	2020-07-06 16:28:58 -07:00
James Cherry	ee326f165c	public headers in include/sta	2020-04-05 14:53:44 -07:00
James Cherry	804953e317	mv public headers to include/sta	2020-04-05 11:35:51 -07:00
James Cherry	4a017e86eb	update copyright	2020-03-06 18:50:37 -08:00
James Cherry	3076b8d2ff	VertexIndex -> VertexId	2019-11-11 09:38:25 -07:00
James Cherry	184d044b02	replace Pool with ObjectTable	2019-11-11 08:28:42 -07:00
James Cherry	3ae920be7d	write_verilog escaped bus name	2019-08-13 21:34:35 -07:00
James Cherry	41ebd34031	leaks	2019-08-12 22:56:32 -07:00
James Cherry	d7248abcab	sdc matches for verilog port nets like \foo[2] [0]	2019-07-04 17:26:14 -07:00
James Cherry	eb9fdd1be0	write verilog match liberty bus bit order	2019-07-02 07:07:34 -07:00
James Cherry	c759feaff6	SdcNetwork leak	2019-07-01 10:26:59 -07:00
James Cherry	8fa2dd674c	SdcNetwork memory error	2019-07-01 07:37:52 -07:00
James Cherry	ed6ed7c74b	g++ compile issue	2019-06-30 22:44:00 -07:00
James Cherry	f34fc4162d	base class destructors public virtual or protected non-virtual	2019-06-30 22:30:53 -07:00
James Cherry	d76ee0ca62	refactor SdcNetwork	2019-06-30 17:17:03 -07:00
James Cherry	e05e7185ba	report_checks transition_time field -> slew	2019-06-24 08:35:04 -07:00
James Cherry	9659c43590	network/sta replaceCell Cell support	2019-06-14 12:05:34 -07:00
James Cherry	895c4c97c1	Sta::insert_buffer	2019-05-03 08:07:00 -07:00
James Cherry	2d519b4740	ucsd 20190410 seg fault accessing/setting power_default_signal_toggle_rate	2019-04-10 20:36:48 -07:00
James Cherry	e5c9bc43fd	2.0.10	2019-03-12 17:25:53 -07:00
James Cherry	92f4968feb	write_path_spice bug fixes	2019-01-20 09:44:24 -08:00
James Cherry	b075ccc783	update copyright	2019-01-01 12:26:11 -08:00
James Cherry	1154fb89fd	and then there was light...	2018-09-28 08:54:21 -07:00