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b31ae3cdbb909bc7b2bfcd9fc63442d32fe25b78
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366 Commits

Author SHA1 Message Date
James Cherry
c671b266fe tidy 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-20 15:02:24 -07:00
James Cherry
6c9af4a5fa LibertyPort::less 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-18 11:39:03 -07:00
James Cherry
668cfb26af makeSceneMap rm dup warnings 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-18 08:45:04 -07:00
James Cherry
6e7ec45bc8 rm extra swig module dcls 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-16 15:46:32 -07:00
James Cherry
134cf2cab7 tidy 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-15 18:21:47 -07:00
James Cherry
63efee64bf tidy round1 2026-04-13 14:59:05 -07:00
James Cherry
6ef92c5fc0 LibertyPort::less 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-10 10:35:36 -07:00
Mike Inouye
d6268da88f Consider multi-bit flops as having sequentials. (#419) 2026-04-10 10:28:01 -07:00
Deepashree Sengupta
c887b2e4b3 Bias pin handling (#409) 
* Update STA to exclude bias pins from timing graph and subsequently in write_verilog

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* unnecessary space in orig verilog

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* Update to use well supplies rather than bias pins

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

---------

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
 2026-04-07 11:00:01 -07:00
James Cherry
f873c6520a Library/Cell name/filename args string_view 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-03 11:22:38 -07:00
James Cherry
9eb9edb0b3 GateTableModel::gateDelay do not clip delays 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-31 14:20:50 -07:00
James Cherry
5955958564 findScaleFactorType, findScaleFactorPvt string_view 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-30 11:01:15 -07:00
James Cherry
1806e4aede StaTclTypes %include "std_string_view.i" 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-28 19:55:13 -07:00
James Cherry
614385fe51 Liberty unnecessary move 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-28 19:48:21 -07:00
James Cherry
6742692876 string squash 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-28 19:13:35 -07:00
James Cherry
b9e439f41c delay calc clip delay to 0.0 resolves #405 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-24 18:42:47 -07:00
Robert O'Callahan
d233581e16 Make wire_load_tree_ default to unknown so we can detect when it's not present in a Liberty file. (#402) 
This is potentially a behavior change, but I think omitting this is rare. I've only seen it in some DTCD Liberty files.
In those Liberty libraries, it seems to be expected that the Liberty data is valid for all `WireloadTree` types.
Thus it is necessary to distinguish between "wire load tree was specified as 'balanced'" and "wire load tree
was not specified".
 2026-03-24 12:35:18 -07:00
James Cherry
464bc3ae4f Report use string instead of string_view 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-18 13:01:05 -07:00
James Cherry
90df0cfea5 LibertyScanner includes 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-18 12:15:57 -07:00
James Cherry
134b547501 use std::format squash 2026-03-16 15:01:38 -07:00
James Cherry
d6e7b4256c lvf squish 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-13 14:06:35 -07:00
James Cherry
00ee6a1956 liberty max_transition warning resolves #403 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-11 11:58:58 -07:00
James Cherry
981f44db68 update copyright 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-10 14:57:45 -07:00
James Cherry
6280635c38 liberty statetable ref test_cell ports resolves #276 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-10 12:58:53 -07:00
James Cherry
0850e97b88 readLibraryAttributes only call when non-empty library 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-09 18:12:56 -07:00
James Cherry
859982bdc7 StdStringSeq -> StringSeq 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-08 15:51:50 -07:00
James Cherry
4f540792a0 rm StringSet 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-08 15:39:41 -07:00
James Cherry
8bd938d840 CheckError use std::string 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-08 15:02:14 -07:00
James Cherry
48511e09b1 override 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-08 14:07:40 -07:00
James Cherry
a419f0a721 LibertyPortPair calls 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-08 13:36:54 -07:00
James Cherry
274637ce46 liberty attributes after cells resolves #400 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-08 10:21:55 -07:00
James Cherry
d8c0e9285b RiseFall use shortName instead of to_string 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-06 12:02:05 -07:00
James Cherry
f1e5587fef rapidus liberty latch D->Q/EN->Q matching 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-05 18:41:25 -07:00
James Cherry
8ed837d74b relevelize latch EN->Q 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-05 13:33:58 -08:00
James Cherry
741bf4d561 rm using std:: 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-02 12:13:13 -08:00
James Cherry
0f8d7cffd3 mv StdStringSeq defs to StringUtil.hh 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-28 15:53:23 -08:00
James Cherry
e76f54a068 rm TokenParser 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-28 15:45:34 -08:00
James Cherry
cd21c43693 rm LibertyPort::clkTreeDelays, clockTreePathDelays 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-28 14:57:00 -08:00
James Cherry
c010a0f99e liberty reader rewrite 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-27 17:12:50 -08:00
James Cherry
4c157f46ee InternalPower::related_pg_port string->port 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-11 08:33:09 -07:00
James Cherry
7cb71fe766 liberty memory management 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-04 18:33:32 -07:00
James Cherry
33e480a6c1 liberty memory management 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-04 18:33:04 -07:00
James Cherry
c7f4bb3bb3 Merge branch 'master' into rel_3.0 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-04 17:36:33 -07:00
James Cherry
cde32a1572 leakage power well pg pin resolves #377 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-04 16:50:28 -07:00
James Cherry
0ae888b619 Merge branch 'master' into rel_3.0 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-03 08:40:58 -07:00
James Cherry
3136871ecd LibertyCell::isClockGateLatchNegedge resolves #375 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-03 08:33:46 -07:00
James Cherry
87ea907884 defineScalingFactorVisitors min_pulse_width resolves #376 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-03 08:18:41 -07:00
James Cherry
b04ffe737b LibertyBuilder::makeRegLatchArcs null ref resolves #368 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-01-20 17:35:25 -07:00
James Cherry
d42b821c00 rel 3.0 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-01-13 09:36:45 -07:00
James Cherry
6ef25d488a more unit issues 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-12-05 14:47:16 -07:00