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20 lines
413 B
Tcl
20 lines
413 B
Tcl
# Test SDC constraint commands
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test1.v
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link_design sdc_test1
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# Create clock
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create_clock -name clk -period 10 [get_ports clk]
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# Set input delay
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set_input_delay -clock clk 2.0 [get_ports in1]
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# Set output delay
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set_output_delay -clock clk 3.0 [get_ports out1]
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# Report clock properties
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report_clock_properties
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# Report checks
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report_checks
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