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b6d598a119
- Add diff_files_sorted to test/helpers.tcl for hash-order-independent SDC comparison (fixes non-deterministic write_sdc output ordering) - Use diff_files_sorted in sdc_derate_disable_deep and sdc_port_delay_advanced tests - Remove stale coverage percentages from test comments (Comment 1) - Remove unnecessary catch blocks in search property tests (Comment 3) - Strengthen load-only tests with actual data verification (Comment 8) - Remove orphan .ok files for deleted monolithic tests (Comment 9) - Add golden .sdcok/.libok/.vok/.sdfok files for SDC/liberty/verilog write-and-diff tests - Add -B (clean rebuild) option to make_coverage_report.sh - Replace (void) casts and EXPECT_TRUE(true) with real assertions in TestSdc.cc and TestVerilog.cc Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
21 lines
1.3 KiB
Plaintext
21 lines
1.3 KiB
Plaintext
###############################################################################
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# Created by write_sdc
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###############################################################################
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current_design sdc_test2
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###############################################################################
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# Timing Constraints
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###############################################################################
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create_clock -name mclk -period 10.0000 [get_ports {clk1}]
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create_generated_clock -name edge_clk -source [get_ports {clk1}] -edges {1 3 5} [get_ports {clk2}]
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set_input_delay 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {in1}]
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set_input_delay 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {in2}]
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set_input_delay 1.5000 -clock [get_clocks {edge_clk}] -add_delay [get_ports {in3}]
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set_output_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {out1}]
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set_output_delay 2.5000 -clock [get_clocks {edge_clk}] -add_delay [get_ports {out2}]
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###############################################################################
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# Environment
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###############################################################################
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###############################################################################
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# Design Rules
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###############################################################################
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