mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-05-30 00:24:12 +08:00
0a3368e177
Use diff_files_sorted for SDC golden file comparisons in disable_case and write_roundtrip_full tests. The upstream set_min_pulse_width output ordering is non-deterministic due to hash map iteration, causing intermittent CI failures. Co-Authored-By: Claude <noreply@anthropic.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
33 lines
1.8 KiB
Plaintext
33 lines
1.8 KiB
Plaintext
###############################################################################
|
|
# Created by write_sdc
|
|
###############################################################################
|
|
current_design sdc_test2
|
|
###############################################################################
|
|
# Timing Constraints
|
|
###############################################################################
|
|
create_clock -name clk1 -period 10.000000 [get_ports {clk1}]
|
|
create_clock -name clk2 -period 20.000000 [get_ports {clk2}]
|
|
set_input_delay 2.000000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
|
|
set_input_delay 2.000000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
|
|
set_input_delay 2.000000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
|
|
set_output_delay 3.000000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
|
|
set_output_delay 3.000000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
|
|
###############################################################################
|
|
# Environment
|
|
###############################################################################
|
|
set_logic_zero [get_ports {in1}]
|
|
set_logic_one [get_ports {in2}]
|
|
set_logic_dc [get_ports {in3}]
|
|
###############################################################################
|
|
# Design Rules
|
|
###############################################################################
|
|
set_min_pulse_width 0.500000 [get_pins {reg1/CK}]
|
|
set_min_pulse_width 0.600000 [get_cells {reg1}]
|
|
set_min_pulse_width -high 0.600000 [get_clocks {clk1}]
|
|
set_min_pulse_width -low 0.400000 [get_clocks {clk1}]
|
|
set_min_pulse_width 0.800000 [get_clocks {clk2}]
|
|
set_max_time_borrow 1.000000 [get_pins {reg1/D}]
|
|
set_max_time_borrow 1.200000 [get_cells {reg2}]
|
|
set_max_time_borrow 2.000000 [get_clocks {clk1}]
|
|
set_max_time_borrow 1.500000 [get_clocks {clk2}]
|