mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
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05e65b1dbf
OpenROAD regression runs 7600+ tests in a shared environment where clock definitions leak between tests. Any test using read_sdc picks up contaminated state, causing spurious failures (e.g., clk2 period 15 vs 20). Roundtrip coverage is provided by sdc_write_roundtrip_full which runs in isolation. Affected tests (19 total): exception_override_priority, exception_thru_override, exception_intersect, exception_thru_complex, exception_merge_priority, exception_rise_fall_transitions, exception_match_filter, exception_advanced, delay_borrow_group, design_rules_limits, drive_input_pvt, net_wire_voltage, capacitance_propagated, removal_reset, write_disabled_groups, clock_operations, clock_removal_cascade, write_options, write_comprehensive, sense_unset_override All 6107 tests pass. Co-Authored-By: Claude <noreply@anthropic.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
199 lines
6.6 KiB
Plaintext
199 lines
6.6 KiB
Plaintext
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg3/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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Startpoint: in3 (input port clocked by clk2)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (ideal)
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2.00 2.00 ^ input external delay
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0.00 2.00 ^ in3 (in)
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0.02 2.02 ^ or1/ZN (OR2_X1)
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0.01 2.03 v nor1/ZN (NOR2_X1)
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0.00 2.03 v reg2/D (DFF_X1)
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2.03 data arrival time
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-2.03 data arrival time
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---------------------------------------------------------
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2.03 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 v reg1/Q (DFF_X1)
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0.00 0.08 v reg3/D (DFF_X1)
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0.08 data arrival time
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg3/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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0.08 slack (MET)
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Startpoint: in1 (input port clocked by clk1)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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2.00 2.00 v input external delay
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0.00 2.00 v in1 (in)
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0.02 2.02 v buf1/Z (BUF_X1)
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0.05 2.07 v or1/ZN (OR2_X1)
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0.03 2.09 ^ nor1/ZN (NOR2_X1)
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0.00 2.09 ^ reg2/D (DFF_X1)
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2.09 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-2.09 data arrival time
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---------------------------------------------------------
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7.87 slack (MET)
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Startpoint: in2 (input port clocked by clk1)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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2.00 2.00 v input external delay
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0.00 2.00 v in2 (in)
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0.01 2.01 ^ inv1/ZN (INV_X1)
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0.03 2.04 ^ and1/ZN (AND2_X1)
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0.01 2.05 v nand1/ZN (NAND2_X1)
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0.00 2.05 v reg1/D (DFF_X1)
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2.05 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-2.05 data arrival time
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---------------------------------------------------------
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7.91 slack (MET)
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Startpoint: in3 (input port clocked by clk2)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk2 (rise edge)
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0.00 0.00 clock network delay (ideal)
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2.00 2.00 v input external delay
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0.00 2.00 v in3 (in)
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0.05 2.05 v or1/ZN (OR2_X1)
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0.03 2.07 ^ nor1/ZN (NOR2_X1)
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0.00 2.07 ^ reg2/D (DFF_X1)
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2.07 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-2.07 data arrival time
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---------------------------------------------------------
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7.89 slack (MET)
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