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9 lines
167 B
Verilog
9 lines
167 B
Verilog
module sdc_test1 (clk, in1, out1);
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input clk, in1;
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output out1;
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wire n1;
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BUF_X1 buf1 (.A(in1), .Z(n1));
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DFF_X1 reg1 (.D(n1), .CK(clk), .Q(out1));
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endmodule
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