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36e516924f
* Add parser support for specify blocks and specparam Treated like regular parameters, and so ignored * Add regression test * Apply PR feedback * missed the verilog_lang
21 lines
277 B
Verilog
21 lines
277 B
Verilog
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module counter(clk, reset, in, out);
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input clk;
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output out;
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input reset;
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input in;
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wire mid;
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parameter PARAM1=1;
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parameter PARAM2="test";
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specify
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specparam SPARAM1=2;
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specparam SPARAM2="test2";
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endspecify
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defparam _1415_.PARAM2 = 1;
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endmodule
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