mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
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fbe9da3fb7
* Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * Incorporated feedbacks from previous version Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * rename tests Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * remove unnecessary newline Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * Updated to use network_->portBitIterator Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> --------- Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
10 lines
393 B
Tcl
10 lines
393 B
Tcl
read_liberty asap7_small.lib.gz
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read_verilog verilog_unconnected_hpin.v
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link_design top
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puts "Find b1/out2: [get_full_name [get_pins b1/out2]]"
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puts "Find b2/out2: [get_full_name [get_pins b2/out2]]"
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# Check if net is connected to "b2/u3/Y" that was the b2/out2 in parent block
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set iterm [sta::find_pin "b2/u3/Y"]
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set net [get_net -of_object [get_pin $iterm]]
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report_net [get_full_name $net]
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