mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-05-30 00:24:12 +08:00
b6d598a119
- Add diff_files_sorted to test/helpers.tcl for hash-order-independent SDC comparison (fixes non-deterministic write_sdc output ordering) - Use diff_files_sorted in sdc_derate_disable_deep and sdc_port_delay_advanced tests - Remove stale coverage percentages from test comments (Comment 1) - Remove unnecessary catch blocks in search property tests (Comment 3) - Strengthen load-only tests with actual data verification (Comment 8) - Remove orphan .ok files for deleted monolithic tests (Comment 9) - Add golden .sdcok/.libok/.vok/.sdfok files for SDC/liberty/verilog write-and-diff tests - Add -B (clean rebuild) option to make_coverage_report.sh - Replace (void) casts and EXPECT_TRUE(true) with real assertions in TestSdc.cc and TestVerilog.cc Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
66 lines
2.0 KiB
Plaintext
66 lines
2.0 KiB
Plaintext
time 1ns
|
|
capacitance 1fF
|
|
resistance 1kohm
|
|
voltage 1v
|
|
current 1mA
|
|
power 1nW
|
|
distance 1um
|
|
Startpoint: data_a[6] (input port clocked by clk)
|
|
Endpoint: carry (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v data_a[6] (in)
|
|
0.06 0.06 v buf_a6/Z (BUF_X1)
|
|
0.03 0.09 v and6/ZN (AND2_X1)
|
|
0.05 0.13 v or_carry/ZN (OR2_X1)
|
|
0.02 0.16 v buf_carry/Z (BUF_X1)
|
|
0.00 0.16 v carry (out)
|
|
0.16 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
0.00 10.00 output external delay
|
|
10.00 data required time
|
|
---------------------------------------------------------
|
|
10.00 data required time
|
|
-0.16 data arrival time
|
|
---------------------------------------------------------
|
|
9.84 slack (MET)
|
|
|
|
|
|
Startpoint: data_b[0] (input port clocked by clk)
|
|
Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ input external delay
|
|
0.00 0.00 ^ data_b[0] (in)
|
|
0.04 0.04 ^ and0/ZN (AND2_X1)
|
|
0.00 0.04 ^ reg0/D (DFF_X1)
|
|
0.04 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg0/CK (DFF_X1)
|
|
0.01 0.01 library hold time
|
|
0.01 data required time
|
|
---------------------------------------------------------
|
|
0.01 data required time
|
|
-0.04 data arrival time
|
|
---------------------------------------------------------
|
|
0.04 slack (MET)
|
|
|
|
|