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15 lines
647 B
Tcl
15 lines
647 B
Tcl
# path_group_names
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read_liberty asap7_small.lib.gz
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read_verilog reg1_asap7.v
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link_design top
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create_clock -name clk -period 500 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 [all_inputs -no_clocks]
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set_output_delay -clock clk 0 [all_outputs]
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puts "Initial path groups: [sta::path_group_names]"
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group_path -name In2Reg -from [all_inputs] -to [all_registers -data_pins]
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group_path -name In2Out -from [all_inputs] -to [all_outputs]
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group_path -name Reg2Out -from [all_registers -clock_pins] -to [all_outputs]
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group_path -name Reg2Reg -from [all_registers -clock_pins] -to [all_registers -data_pins]
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puts "Final path groups: [sta::path_group_names]"
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