James Cherry 74e287a7eb write_verilog escaped bus port name "input [7:0] \in[0] ;"

2019-07-03 21:18:38 -07:00

..

Makefile.am

cmake, write_path_spice

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Verilog.i

write_verilog escaped bus port name "input [7:0] \in[0] ;"

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Verilog.tcl

write_verilog -sorted -> -sort

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VerilogLex.ll

link_design use verilog library to lookup top

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VerilogParse.yy

link_design use verilog library to lookup top

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VerilogReader.cc

write_verilog escaped bus port name "input [7:0] \in[0] ;"

2019-07-03 21:18:38 -07:00

VerilogReader.hh

rm redundant StaState args

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VerilogReaderPvt.hh

link_design use verilog library to lookup top

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VerilogWriter.cc

write_verilog escaped bus port name "input [7:0] \in[0] ;"

2019-07-03 21:18:38 -07:00

VerilogWriter.hh

write_verilog -sorted -> -sort

2019-06-17 12:33:37 -07:00