Logo
Explore Help
Register Sign In
The-OpenROAD-Project/OpenSTA
1
0
Fork 0
You've already forked OpenSTA
mirror of https://github.com/The-OpenROAD-Project/OpenSTA.git synced 2026-05-30 00:24:12 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity
Files
184d044b0296e033ff796f1352f2b7010c707a20
OpenSTA/verilog
History
James Cherry 74e287a7eb write_verilog escaped bus port name "input [7:0] \in[0] ;"
2019-07-03 21:18:38 -07:00
..
Makefile.am
cmake, write_path_spice
2019-01-03 16:14:15 -08:00
Verilog.i
write_verilog escaped bus port name "input [7:0] \in[0] ;"
2019-07-03 21:18:38 -07:00
Verilog.tcl
write_verilog -sorted -> -sort
2019-06-17 12:33:37 -07:00
VerilogLex.ll
link_design use verilog library to lookup top
2019-06-26 16:01:58 -07:00
VerilogParse.yy
link_design use verilog library to lookup top
2019-06-26 16:01:58 -07:00
VerilogReader.cc
write_verilog escaped bus port name "input [7:0] \in[0] ;"
2019-07-03 21:18:38 -07:00
VerilogReader.hh
rm redundant StaState args
2019-06-17 08:32:28 -07:00
VerilogReaderPvt.hh
link_design use verilog library to lookup top
2019-06-26 16:01:58 -07:00
VerilogWriter.cc
write_verilog escaped bus port name "input [7:0] \in[0] ;"
2019-07-03 21:18:38 -07:00
VerilogWriter.hh
write_verilog -sorted -> -sort
2019-06-17 12:33:37 -07:00
Powered by Gitea Version: 1.25.4 Page: 502ms Template: 1ms
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API