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https://github.com/The-OpenROAD-Project/OpenSTA.git
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70d52c2fe0
* Add `has_memory` property * Whitespace fixes * Remove unused argument name * Review fixes * Move gf180mcu_sram.lib.gz from examples/ to test/ * Fix tcl script * Switch to is_memory * Remove is_memory_cell
36 lines
496 B
Verilog
36 lines
496 B
Verilog
module get_is_memory (
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input CLK,
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input CEN,
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input GWEN,
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input [7:0] WEN,
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input [6:0] A,
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input [7:0] D,
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output [7:0] Q
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);
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wire CEN_buf;
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wire GWEN_reg;
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BUFx2_ASAP7_75t_R buf_inst (
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.A(CEN),
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.Y(CEN_buf)
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);
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DFFHQx4_ASAP7_75t_R dff_inst (
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.CLK(CLK),
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.D(GWEN),
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.Q(GWEN_reg)
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);
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gf180mcu_fd_ip_sram__sram128x8m8wm1 sram_inst (
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.CLK(CLK),
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.CEN(CEN_buf),
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.GWEN(GWEN_reg),
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.WEN(WEN),
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.A(A),
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.D(D),
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.Q(Q)
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);
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endmodule
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