mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
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b6d598a119
- Add diff_files_sorted to test/helpers.tcl for hash-order-independent SDC comparison (fixes non-deterministic write_sdc output ordering) - Use diff_files_sorted in sdc_derate_disable_deep and sdc_port_delay_advanced tests - Remove stale coverage percentages from test comments (Comment 1) - Remove unnecessary catch blocks in search property tests (Comment 3) - Strengthen load-only tests with actual data verification (Comment 8) - Remove orphan .ok files for deleted monolithic tests (Comment 9) - Add golden .sdcok/.libok/.vok/.sdfok files for SDC/liberty/verilog write-and-diff tests - Add -B (clean rebuild) option to make_coverage_report.sh - Replace (void) casts and EXPECT_TRUE(true) with real assertions in TestSdc.cc and TestVerilog.cc Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
181 lines
4.9 KiB
Plaintext
181 lines
4.9 KiB
Plaintext
--- redirect + log simultaneously ---
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No differences found.
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No differences found.
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--- gzipped liberty read ---
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--- trigger warn paths ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.32 0.32 ^ reg1/Q (DFF_X1)
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0.00 0.32 ^ out1 (out)
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0.32 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.32 data arrival time
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---------------------------------------------------------
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9.68 slack (MET)
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--- debug check path coverage ---
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Library: NangateOpenCellLibrary
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Cell: BUF_X1
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Arc sense: positive_unate
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Arc type: combinational
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A ^ -> Z ^
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delay_calc: find delays to level 50
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delay_calc: find delays reg1/Q (DFF_X1)
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delay_calc: find delays out1 (dcalc_test1)
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delay_calc: found 2 delays
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P = 1.00 V = 1.10 T = 25.00
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------- input_net_transition = 0.00
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| total_output_net_capacitance = 1.70
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| 0.37 1.90
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v --------------------
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0.00 | 0.02 0.02
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0.00 | 0.02 0.02
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Table value = 0.02
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PVT scale factor = 1.00
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Delay = 0.02
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------- input_net_transition = 0.00
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| total_output_net_capacitance = 1.70
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| 0.37 1.90
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v --------------------
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0.00 | 0.00 0.01
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0.00 | 0.00 0.01
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Table value = 0.01
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PVT scale factor = 1.00
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Slew = 0.01
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Driver waveform slew = 0.01
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.............................................
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A v -> Z v
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delay_calc: find delays to level 50
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delay_calc: found 0 delays
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P = 1.00 V = 1.10 T = 25.00
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------- input_net_transition = 0.00
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| total_output_net_capacitance = 1.55
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| 0.37 1.90
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v --------------------
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0.00 | 0.02 0.02
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0.00 | 0.02 0.03
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Table value = 0.02
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PVT scale factor = 1.00
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Delay = 0.02
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------- input_net_transition = 0.00
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| total_output_net_capacitance = 1.55
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| 0.37 1.90
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v --------------------
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0.00 | 0.00 0.01
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0.00 | 0.00 0.01
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Table value = 0.01
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PVT scale factor = 1.00
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Slew = 0.01
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Driver waveform slew = 0.01
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.............................................
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dcalc with debug: done
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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--- multiple redirect cycles ---
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--- string redirect cycles ---
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s1 len: 95
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s2 len: 883
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s3 len: 1866
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--- report_line coverage ---
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test line 1
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test line with special chars: [ ] { }
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--- format functions edge cases ---
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format_time(0): 0.000
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format_time(-1ns): -1.000
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format_time(1us, 6 digits): 1000.000000
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format_capacitance(0): 0.000
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format_capacitance(1nF): 999999.938
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format_resistance(0): 0.000
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format_resistance(1MOhm): 1000.000
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format_power(0): 0.000
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format_power(1W): 1000000000.000
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--- set_cmd_units edge cases ---
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time 1ps
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capacitance 1fF
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resistance 1kohm
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voltage 1v
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current 1mA
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power 1nW
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distance 1um
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time 1us
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capacitance 1fF
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resistance 1kohm
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voltage 1v
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current 1mA
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power 1nW
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distance 1um
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--- suppress_msg exercising suppressed check ---
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