mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-05-30 00:24:12 +08:00
c887b2e4b3
* Update STA to exclude bias pins from timing graph and subsequently in write_verilog Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * unnecessary space in orig verilog Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * Update to use well supplies rather than bias pins Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> --------- Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
27 lines
316 B
Plaintext
27 lines
316 B
Plaintext
module top (y,
|
|
a);
|
|
output y;
|
|
input a;
|
|
|
|
|
|
sky130_fd_sc_hd__buf_1 u1 (.A(a),
|
|
.X(y));
|
|
endmodule
|
|
module top (y,
|
|
a);
|
|
output y;
|
|
input a;
|
|
|
|
wire VGND;
|
|
wire VNB;
|
|
wire VPB;
|
|
wire VPWR;
|
|
|
|
sky130_fd_sc_hd__buf_1 u1 (.VGND(VGND),
|
|
.VNB(VNB),
|
|
.VPB(VPB),
|
|
.VPWR(VPWR),
|
|
.A(a),
|
|
.X(y));
|
|
endmodule
|