mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
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44e7316da1
* Add {`inst`, `cell`, `src`, `nets`} to `report_checks -format json`
* Smallfix
* Improved nets
* Race condition fix
* Fixes
* Small whitespace fix
* Add no paths corner case stuff
* Adjustments to naming of fields
* Requested fixes
* Reintroduce escapeBackslashes, use stringCopy to prevent stack memory warning
* Fix escapeBackslashes to use preferred style
* No backslash escaping
* Make requested fixes
31 lines
785 B
Verilog
31 lines
785 B
Verilog
/* Generated by Yosys 0.8+ */
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(* hdlname = "\\counter" *)
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(* top = 1 *)
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(* src = "synthesis/tests/counter.v:16.1-32.10" *)
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module counter(clk, reset, in, out);
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(* src = "synthesis/tests/counter.v:17.14-17.17" *)
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input clk;
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(* src = "synthesis/tests/counter.v:19.18-19.21" *)
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output out;
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(* src = "synthesis/tests/counter.v:18.14-18.19" *)
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input reset;
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input in;
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wire mid;
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(* bottom_bound = 1'sh0 *)
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(* src = "synthesis/tests/counter.v:22.3-28.6", attr1 = "test_attr1", attr2 = "test_attr2" *)
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sky130_fd_sc_hd__dfrtp_1 _1415_ (
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.CLK(clk),
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.D(in),
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.Q(mid),
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.RESET_B(reset)
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);
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(* src = "synthesis/tests/counter.v:22.3-28.6" *)
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sky130_fd_sc_hd__dfrtp_1 \_1416_[0] (
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.CLK(clk),
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.D(mid),
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.Q(out),
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.RESET_B(reset)
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);
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endmodule
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