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https://github.com/The-OpenROAD-Project/OpenSTA.git
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fbe9da3fb7
* Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * Incorporated feedbacks from previous version Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * rename tests Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * remove unnecessary newline Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * Updated to use network_->portBitIterator Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> --------- Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
25 lines
795 B
Verilog
25 lines
795 B
Verilog
module top (in, clk1, clk2, out, out2);
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input in, clk1, clk2;
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output out, out2;
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block1 b1 (.in(in), .clk(clk1), .out(b1out), .out2(out2));
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block2 b2 (.in(b1out), .clk(clk2), .out(out));
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endmodule // top
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module block1 (in, clk, out, out2);
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input in, clk;
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output out, out2;
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BUFx2_ASAP7_75t_R u1 (.A(in), .Y(u1out));
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DFFHQx4_ASAP7_75t_R r1 (.D(u1out), .CLK(clk), .Q(r1q));
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BUFx2_ASAP7_75t_R u2 (.A(r1q), .Y(out));
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BUFx2_ASAP7_75t_R u3 (.A(out), .Y(out2));
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endmodule // block1
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module block2 (in, clk, out, out2);
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input in, clk;
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output out, out2;
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BUFx2_ASAP7_75t_R u1 (.A(in), .Y(u1out));
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DFFHQx4_ASAP7_75t_R r1 (.D(u1out), .CLK(clk), .Q(r1q));
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BUFx2_ASAP7_75t_R u2 (.A(r1q), .Y(out));
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BUFx2_ASAP7_75t_R u3 (.A(out), .Y(out2));
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endmodule // block2
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