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9 lines
164 B
Verilog
9 lines
164 B
Verilog
module graph_test1 (clk, d, q);
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input clk, d;
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output q;
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wire n1;
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DFF_X1 reg1 (.D(d), .CK(clk), .Q(n1));
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DFF_X1 reg2 (.D(n1), .CK(clk), .Q(q));
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endmodule
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