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OpenSTA/verilog
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ambd161 36e516924f Recognize some basic specify blocks and ignore them (#309) 
* Add parser support for specify blocks and specparam
Treated like regular parameters, and so ignored

* Add regression test

* Apply PR feedback

* missed the verilog_lang
2025-10-12 14:11:00 -07:00
..
Verilog.i
update copyright
2025-01-21 18:54:33 -07:00
Verilog.tcl
update copyright
2025-01-21 18:54:33 -07:00
VerilogLex.ll
Recognize some basic specify blocks and ignore them (#309)
2025-10-12 14:11:00 -07:00
VerilogParse.yy
Recognize some basic specify blocks and ignore them (#309)
2025-10-12 14:11:00 -07:00
VerilogReader.cc
remove using std from headers
2025-04-11 16:59:48 -07:00
VerilogReader.hh
remove using std from headers
2025-04-11 16:59:48 -07:00
VerilogReaderPvt.hh
remove using std from headers
2025-04-11 16:59:48 -07:00
VerilogScanner.hh
LibExpr/spef/saif c++ parsers
2025-02-01 14:49:30 -08:00
VerilogWriter.cc
remove using std from headers
2025-04-11 16:59:48 -07:00