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https://github.com/The-OpenROAD-Project/OpenSTA.git
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c887b2e4b3
* Update STA to exclude bias pins from timing graph and subsequently in write_verilog Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * unnecessary space in orig verilog Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * Update to use well supplies rather than bias pins Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> --------- Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
18 lines
247 B
Verilog
18 lines
247 B
Verilog
module top (
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output y,
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input a
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);
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supply1 VPWR;
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supply0 VGND;
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supply1 VPB;
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supply0 VNB;
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sky130_fd_sc_hd__buf_1 u1 (
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.X(y),
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.A(a),
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.VPWR(VPWR),
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.VGND(VGND),
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.VPB(VPB),
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.VNB(VNB)
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);
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endmodule
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