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https://github.com/The-OpenROAD-Project/OpenSTA.git
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30 lines
994 B
Plaintext
30 lines
994 B
Plaintext
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r2/CK (DFF_X1)
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1.10 1.10 v r2/Q (DFF_X1)
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1.10 2.20 v u1/Z (BUF_X1)
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1.10 3.30 v u2/ZN (AND2_X1)
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0.00 3.30 v r3/D (DFF_X1)
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3.30 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r3/CK (DFF_X1)
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-0.50 9.50 library setup time
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9.50 data required time
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---------------------------------------------------------
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9.50 data required time
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-3.30 data arrival time
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---------------------------------------------------------
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6.20 slack (MET)
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