Files
OpenSTA/parasitics/ReduceParasitics.cc
James Cherry f6253af8a9 ccs ceff delay calc
commit 87130be63ddbf1a7fb65986b02839eb4c0b13168
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Feb 27 09:49:02 2024 -0700

    ccs ceff delay calc

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit de0dd38dabda2f7ef51b49c196c2787a0d3c5784
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Feb 27 07:40:11 2024 -0700

    dcalc public funcs

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit dd7fcb12f929b9b0a391653cad42e617f9cbdd3b
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Feb 26 09:08:37 2024 -0700

    mv CircuitSim.hh to include

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 9663e46d28ece544ee1453f229990c9db9e0efec
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Feb 25 17:58:57 2024 -0700

    ArcDcalcArg

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 76b0588034faaefd2302c865c441975f76386d3f
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Feb 25 15:36:46 2024 -0700

    ensureVoltageWaveforms

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit f88e67b861c56752e5b36efe2b552ba0077a7180
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Feb 25 15:00:02 2024 -0700

    const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 8f32cc571dcadee0185b08f951a1f79d46e7984d
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Feb 25 14:57:51 2024 -0700

    Graph::gateEdgeArc

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit ac3cb35cb6732d7ecbf0532d7351a3ff2a917fc9
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Feb 25 14:31:30 2024 -0700

    ConcreteParasiticSubNodeMap, ConcreteParasiticPinNodeMap use id cmp

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit cbfe4eac463036c26a64701239d7651d91a09778
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Feb 25 14:08:41 2024 -0700

    WriteSpice

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 8b5d30f1a8b1ccb8c9cbd9d7ba93418907c41b2a
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Feb 24 09:45:46 2024 -0700

    emplace_push

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 5335a2eaaf737ed7c7a8cff30654a68c4ac4c8e4
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Feb 23 16:19:30 2024 -0700

    Parasitics::findParasiticNode

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit ce92f3caf28afb0e0384799f08166cfb0aecfea0
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Feb 23 15:53:28 2024 -0700

    Parasitics::findParasiticNode

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 0c591430c725a3ebd50d2892673dca76e023dc32
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Feb 23 09:03:18 2024 -0700

    Parsitics::name(node) const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 499c297e64d1487388f549843ff9ea05e8555cfc
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Feb 23 09:03:07 2024 -0700

    write_spice umr

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 6984c398dbce9e6266fab8377a844bc518481d9d
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Feb 22 18:42:34 2024 -0700

    gcc warning

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit edec16519806013623194d8201e804dec81a51dd
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Feb 22 17:54:11 2024 -0700

    no cuddification

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 4a0e1070c179b2f8615b604c362359ce4b3a0e2e
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Feb 22 17:29:46 2024 -0700

    sim const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 2e941fafa631f6b9bc0f82784b9146de2449e9c5
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Feb 22 17:29:39 2024 -0700

    sdc comment

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 1c12f56aee7115fcb06807b5b6c626d1a419ccdc
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Feb 21 13:13:29 2024 -0700

    Sim use Bdd class

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit b70c41d5caec56c3001b834141b6dab89bb933ed
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Feb 20 12:18:27 2024 -0700

    write_spice coupling caps

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 614d2cd41a1a9cf850dbe480954a5f58ee0dc21e
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Feb 19 14:37:30 2024 -0700

    write_spice time offset

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit f0ba1fca0dfca384e6fb0be302bba9ced71ee41c
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Feb 19 10:59:18 2024 -0700

    class Bdd for cudd

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 24c94756334fce5e70e97ce0ee31375ae4e59b84
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Feb 18 08:58:30 2024 -0700

    WriteSpice

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 47a4505d88bdfe4a85056895f8b7d842e07dce8d
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Feb 16 21:34:23 2024 -0700

    default sim ngspice

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 06e279555a076e218f0a9c308e8937a6fc8fdea4
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Feb 16 21:34:01 2024 -0700

    WriteSpice refactor

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 06e3f0734edbbbd69ad063e97d1d8cca92a83aea
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Feb 15 15:18:35 2024 -0700

    mv report_dcalc to DelayCalc.tcl

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 922056471a6d380699bbd0623f95637401d23eff
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Feb 15 14:27:31 2024 -0700

    WriteSpice::cell_spice_port_names_

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 732922ead68097e3f7da268ecc5ae2ca2daa4492
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Feb 15 13:35:13 2024 -0700

    WritePathSpice.hh

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 8cd6e2ffc6ad66e831630273b5eacd192259191e
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Feb 15 10:11:39 2024 -0700

    small

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit f7f6bfb49f43ddc3e45c294f89c8814d60df5220
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Feb 15 09:48:09 2024 -0700

    refactor WritePathSpice

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit f74db730c3e8c67a24d531266510e4376db463d3
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Feb 14 09:22:01 2024 -0700

    Sta.hh

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 051532deef203cae97e32e8af7a2348bfd8912cc
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Feb 14 08:14:44 2024 -0700

    PowerClass.hh

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit bfb8357d1093e5d3da14e708acd21fc21ba3b0dd
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Feb 14 08:08:56 2024 -0700

    doc

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 8fe28ec91b234d9d8210019aa46a2e8107aa497a
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Feb 14 07:32:34 2024 -0700

    ClkSkew use seq instead of set

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit c4e3a3a0315ab4f6160a707e838423bb734f5363
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Feb 13 19:26:45 2024 -0700

    report_clock_latency

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 51fb6657d9706c7443e1c269cfe63cf080b05d50
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Feb 13 11:10:11 2024 -0700

    report_clock_latency

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit e639ee129d13e1c11b34bca0762b8136b18563f3
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Feb 12 11:19:06 2024 -0700

    ClkSkew use map

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit e91d3ea8142a73b7b607dfdf53b3fce8e2f16984
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Feb 12 10:18:27 2024 -0700

    report_clock_skew report format

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit c650b7ec63b83382ba9cec7d187ffee8a031c2ce
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Feb 12 09:22:29 2024 -0700

    report_clock_skew include macro clock_tree_path_delay

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit cf14b230a9944b95ba43ef7c09e553d9014990eb
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Feb 11 11:03:29 2024 -0700

    clk skew range iter

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit e7e0342e063ac876d00d03fd1ff0eab1715cfde4
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Feb 11 08:11:29 2024 -0700

    write_spice sensitize and3

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 743ceb676c763ac5bcbf05e630a4da1b507c537d
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Feb 10 18:07:04 2024 -0700

    write spice

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

Signed-off-by: James Cherry <cherry@parallaxsw.com>
2024-02-27 10:00:48 -07:00

697 lines
21 KiB
C++

// OpenSTA, Static Timing Analyzer
// Copyright (c) 2024, Parallax Software, Inc.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
#include "ReduceParasitics.hh"
#include "Error.hh"
#include "Debug.hh"
#include "MinMax.hh"
#include "Liberty.hh"
#include "Network.hh"
#include "Sdc.hh"
#include "Corner.hh"
#include "Parasitics.hh"
namespace sta {
using std::max;
typedef Map<ParasiticNode*, double> ParasiticNodeValueMap;
typedef Map<ParasiticResistor*, double> ResistorCurrentMap;
typedef Set<ParasiticResistor*> ParasiticResistorSet;
typedef Set<ParasiticNode*> ParasiticNodeSet;
class ReduceToPi : public StaState
{
public:
ReduceToPi(StaState *sta);
void reduceToPi(const Parasitic *parasitic_network,
const Pin *drvr_pin,
ParasiticNode *drvr_node,
float coupling_cap_factor,
const RiseFall *rf,
const Corner *corner,
const MinMax *min_max,
const ParasiticAnalysisPt *ap,
float &c2,
float &rpi,
float &c1);
bool pinCapsOneValue() { return pin_caps_one_value_; }
protected:
void reducePiDfs(const Pin *drvr_pin,
ParasiticNode *node,
ParasiticResistor *from_res,
double src_resistance,
double &y1,
double &y2,
double &y3,
double &dwn_cap,
double &max_resistance);
void visit(ParasiticNode *node);
bool isVisited(ParasiticNode *node);
void leave(ParasiticNode *node);
void setDownstreamCap(ParasiticNode *node,
float cap);
float downstreamCap(ParasiticNode *node);
float pinCapacitance(ParasiticNode *node);
bool isLoopResistor(ParasiticResistor *resistor);
void markLoopResistor(ParasiticResistor *resistor);
bool includes_pin_caps_;
float coupling_cap_multiplier_;
const RiseFall *rf_;
const Corner *corner_;
const MinMax *min_max_;
const ParasiticAnalysisPt *ap_;
ParasiticNodeResistorMap resistor_map_;
ParasiticNodeCapacitorMap capacitor_map_;
ParasiticNodeSet visited_nodes_;
ParasiticNodeValueMap node_values_;
ParasiticResistorSet loop_resistors_;
bool pin_caps_one_value_;
};
ReduceToPi::ReduceToPi(StaState *sta) :
StaState(sta),
coupling_cap_multiplier_(1.0),
rf_(nullptr),
corner_(nullptr),
min_max_(nullptr),
pin_caps_one_value_(true)
{
}
// "Modeling the Driving-Point Characteristic of Resistive
// Interconnect for Accurate Delay Estimation", Peter O'Brien and
// Thomas Savarino, Proceedings of the 1989 Design Automation
// Conference.
void
ReduceToPi::reduceToPi(const Parasitic *parasitic_network,
const Pin *drvr_pin,
ParasiticNode *drvr_node,
float coupling_cap_factor,
const RiseFall *rf,
const Corner *corner,
const MinMax *min_max,
const ParasiticAnalysisPt *ap,
float &c2,
float &rpi,
float &c1)
{
includes_pin_caps_ = parasitics_->includesPinCaps(parasitic_network),
coupling_cap_multiplier_ = coupling_cap_factor;
rf_ = rf;
corner_ = corner;
min_max_ = min_max;
ap_ = ap;
resistor_map_ = parasitics_->parasiticNodeResistorMap(parasitic_network);
capacitor_map_ = parasitics_->parasiticNodeCapacitorMap(parasitic_network);
double y1, y2, y3, dcap;
double max_resistance = 0.0;
reducePiDfs(drvr_pin, drvr_node, nullptr, 0.0,
y1, y2, y3, dcap, max_resistance);
if (y2 == 0.0 && y3 == 0.0) {
// Capacitive load.
c1 = y1;
c2 = 0.0;
rpi = 0.0;
}
else {
c1 = y2 * y2 / y3;
c2 = y1 - y2 * y2 / y3;
rpi = -y3 * y3 / (y2 * y2 * y2);
}
debugPrint(debug_, "parasitic_reduce", 2,
" Pi model c2=%.3g rpi=%.3g c1=%.3g max_r=%.3g",
c2, rpi, c1, max_resistance);
}
// Find admittance moments.
void
ReduceToPi::reducePiDfs(const Pin *drvr_pin,
ParasiticNode *node,
ParasiticResistor *from_res,
double src_resistance,
double &y1,
double &y2,
double &y3,
double &dwn_cap,
double &max_resistance)
{
if (parasitics_->isExternal(node)) {
y1 = y2 = y3 = 0.0;
max_resistance = 0.0;
dwn_cap = 0.0;
}
else {
double coupling_cap = 0.0;
ParasiticCapacitorSeq &capacitors = capacitor_map_[node];
for (ParasiticCapacitor *capacitor : capacitors)
coupling_cap += parasitics_->value(capacitor);
dwn_cap = parasitics_->nodeGndCap(node)
+ coupling_cap * coupling_cap_multiplier_
+ pinCapacitance(node);
y1 = dwn_cap;
y2 = y3 = 0.0;
max_resistance = max(max_resistance, src_resistance);
visit(node);
ParasiticResistorSeq &resistors = resistor_map_[node];
for (ParasiticResistor *resistor : resistors) {
if (!isLoopResistor(resistor)) {
ParasiticNode *onode = parasitics_->otherNode(resistor, node);
// One commercial extractor creates resistors with identical from/to nodes.
if (onode != node
&& resistor != from_res) {
if (isVisited(onode)) {
// Resistor loop.
debugPrint(debug_, "parasitic_reduce", 2, " loop detected thru resistor %lu",
parasitics_->id(resistor));
markLoopResistor(resistor);
}
else {
double r = parasitics_->value(resistor);
double yd1, yd2, yd3, dcap;
reducePiDfs(drvr_pin, onode, resistor, src_resistance + r,
yd1, yd2, yd3, dcap, max_resistance);
// Rule 3. Upstream traversal of a series resistor.
// Rule 4. Parallel admittances add.
y1 += yd1;
y2 += yd2 - r * yd1 * yd1;
y3 += yd3 - 2 * r * yd1 * yd2 + r * r * yd1 * yd1 * yd1;
dwn_cap += dcap;
}
}
}
}
setDownstreamCap(node, dwn_cap);
leave(node);
debugPrint(debug_, "parasitic_reduce", 3,
" node %s y1=%.3g y2=%.3g y3=%.3g cap=%.3g",
parasitics_->name(node), y1, y2, y3, dwn_cap);
}
}
float
ReduceToPi::pinCapacitance(ParasiticNode *node)
{
const Pin *pin = parasitics_->pin(node);
float pin_cap = 0.0;
if (pin) {
Port *port = network_->port(pin);
LibertyPort *lib_port = network_->libertyPort(port);
if (lib_port) {
if (!includes_pin_caps_) {
pin_cap = sdc_->pinCapacitance(pin, rf_, corner_, min_max_);
pin_caps_one_value_ &= lib_port->capacitanceIsOneValue();
}
}
else if (network_->isTopLevelPort(pin))
pin_cap = sdc_->portExtCap(port, rf_, corner_, min_max_);
}
return pin_cap;
}
void
ReduceToPi::visit(ParasiticNode *node)
{
visited_nodes_.insert(node);
}
bool
ReduceToPi::isVisited(ParasiticNode *node)
{
return visited_nodes_.hasKey(node);
}
void
ReduceToPi::leave(ParasiticNode *node)
{
visited_nodes_.erase(node);
}
bool
ReduceToPi::isLoopResistor(ParasiticResistor *resistor)
{
return loop_resistors_.hasKey(resistor);
}
void
ReduceToPi::markLoopResistor(ParasiticResistor *resistor)
{
loop_resistors_.insert(resistor);
}
void
ReduceToPi::setDownstreamCap(ParasiticNode *node,
float cap)
{
node_values_[node] = cap;
}
float
ReduceToPi::downstreamCap(ParasiticNode *node)
{
return node_values_[node];
}
////////////////////////////////////////////////////////////////
class ReduceToPiElmore : public ReduceToPi
{
public:
ReduceToPiElmore(StaState *sta);
Parasitic *makePiElmore(const Parasitic *parasitic_network,
const Pin *drvr_pin,
ParasiticNode *drvr_node,
float coupling_cap_factor,
const RiseFall *rf,
const Corner *corner,
const MinMax *min_max,
const ParasiticAnalysisPt *ap);
void reduceElmoreDfs(const Pin *drvr_pin,
ParasiticNode *node,
ParasiticResistor *from_res,
double elmore,
Parasitic *pi_elmore);
};
Parasitic *
reduceToPiElmore(const Parasitic *parasitic_network,
const Pin *drvr_pin,
const RiseFall *rf,
float coupling_cap_factor,
const Corner *corner,
const MinMax *min_max,
const ParasiticAnalysisPt *ap,
StaState *sta)
{
Parasitics *parasitics = sta->parasitics();
ParasiticNode *drvr_node =
parasitics->findParasiticNode(parasitic_network, drvr_pin);
if (drvr_node) {
debugPrint(sta->debug(), "parasitic_reduce", 1, "Reduce driver %s %s %s",
sta->network()->pathName(drvr_pin),
rf->asString(),
min_max->asString());
ReduceToPiElmore reducer(sta);
return reducer.makePiElmore(parasitic_network, drvr_pin, drvr_node,
coupling_cap_factor, rf, corner,
min_max, ap);
}
return nullptr;
}
ReduceToPiElmore::ReduceToPiElmore(StaState *sta) :
ReduceToPi(sta)
{
}
Parasitic *
ReduceToPiElmore::makePiElmore(const Parasitic *parasitic_network,
const Pin *drvr_pin,
ParasiticNode *drvr_node,
float coupling_cap_factor,
const RiseFall *rf,
const Corner *corner,
const MinMax *min_max,
const ParasiticAnalysisPt *ap)
{
float c2, rpi, c1;
reduceToPi(parasitic_network, drvr_pin, drvr_node, coupling_cap_factor,
rf, corner, min_max, ap, c2, rpi, c1);
Parasitic *pi_elmore = parasitics_->makePiElmore(drvr_pin, rf, ap,
c2, rpi, c1);
parasitics_->setIsReducedParasiticNetwork(pi_elmore, true);
reduceElmoreDfs(drvr_pin, drvr_node, 0, 0.0, pi_elmore);
return pi_elmore;
}
// Find elmore delays on 2nd DFS search using downstream capacitances
// set by reducePiDfs.
void
ReduceToPiElmore::reduceElmoreDfs(const Pin *drvr_pin,
ParasiticNode *node,
ParasiticResistor *from_res,
double elmore,
Parasitic *pi_elmore)
{
const Pin *pin = parasitics_->pin(node);
if (from_res && pin) {
if (network_->isLoad(pin)) {
debugPrint(debug_, "parasitic_reduce", 2, " Load %s elmore=%.3g",
network_->pathName(pin),
elmore);
parasitics_->setElmore(pi_elmore, pin, elmore);
}
}
visit(node);
ParasiticResistorSeq &resistors = resistor_map_[node];
for (ParasiticResistor *resistor : resistors) {
ParasiticNode *onode = parasitics_->otherNode(resistor, node);
if (resistor != from_res
&& !isVisited(onode)
&& !isLoopResistor(resistor)) {
float r = parasitics_->value(resistor);
double onode_elmore = elmore + r * downstreamCap(onode);
reduceElmoreDfs(drvr_pin, onode, resistor, onode_elmore, pi_elmore);
}
}
leave(node);
}
////////////////////////////////////////////////////////////////
class ReduceToPiPoleResidue2 : public ReduceToPi
{
public:
ReduceToPiPoleResidue2(StaState *sta);
~ReduceToPiPoleResidue2();
void findPolesResidues(const Parasitic *parasitic_network,
Parasitic *pi_pole_residue,
const Pin *drvr_pin,
ParasiticNode *drvr_node);
Parasitic *makePiPoleResidue2(const Parasitic *parasitic_network,
const Pin *drvr_pin,
ParasiticNode *drvr_node,
float coupling_cap_factor,
const RiseFall *rf,
const Corner *corner,
const MinMax *min_max,
const ParasiticAnalysisPt *ap);
private:
void findMoments(const Pin *drvr_pin,
ParasiticNode *drvr_node,
int moment_count);
void findMoments(const Pin *drvr_pin,
ParasiticNode *node,
double from_volt,
ParasiticResistor *from_res,
int moment_index);
double findBranchCurrents(const Pin *drvr_pin,
ParasiticNode *node,
ParasiticResistor *from_res,
int moment_index);
double moment(ParasiticNode *node,
int moment_index);
void setMoment(ParasiticNode *node,
double moment,
int moment_index);
double current(ParasiticResistor *res);
void setCurrent(ParasiticResistor *res,
double i);
void findPolesResidues(Parasitic *pi_pole_residue,
const Pin *drvr_pin,
const Pin *load_pin,
ParasiticNode *load_node);
// Resistor/capacitor currents.
ResistorCurrentMap currents_;
ParasiticNodeValueMap *moments_;
};
ReduceToPiPoleResidue2::ReduceToPiPoleResidue2(StaState *sta) :
ReduceToPi(sta),
moments_(nullptr)
{
}
// The interconnect moments are found using RICE.
// "RICE: Rapid Interconnect Circuit Evaluation Using AWE",
// Curtis Ratzlaff and Lawrence Pillage, IEEE Transactions on
// Computer-Aided Design of Integrated Circuits and Systems,
// Vol 13, No 6, June 1994, pg 763-776.
//
// The poles and residues are found using these algorithms.
// "An Explicit RC-Circuit Delay Approximation Based on the First
// Three Moments of the Impulse Response", Proceedings of the 33rd
// Design Automation Conference, 1996, pg 611-616.
Parasitic *
reduceToPiPoleResidue2(const Parasitic *parasitic_network,
const Pin *drvr_pin,
const RiseFall *rf,
float coupling_cap_factor,
const Corner *corner,
const MinMax *min_max,
const ParasiticAnalysisPt *ap,
StaState *sta)
{
Parasitics *parasitics = sta->parasitics();
ParasiticNode *drvr_node =
parasitics->findParasiticNode(parasitic_network, drvr_pin);
if (drvr_node) {
debugPrint(sta->debug(), "parasitic_reduce", 1, "Reduce driver %s",
sta->network()->pathName(drvr_pin));
ReduceToPiPoleResidue2 reducer(sta);
return reducer.makePiPoleResidue2(parasitic_network, drvr_pin, drvr_node,
coupling_cap_factor, rf,
corner, min_max, ap);
}
return nullptr;
}
Parasitic *
ReduceToPiPoleResidue2::makePiPoleResidue2(const Parasitic *parasitic_network,
const Pin *drvr_pin,
ParasiticNode *drvr_node,
float coupling_cap_factor,
const RiseFall *rf,
const Corner *corner,
const MinMax *min_max,
const ParasiticAnalysisPt *ap)
{
float c2, rpi, c1;
reduceToPi(parasitic_network, drvr_pin, drvr_node,
coupling_cap_factor, rf, corner, min_max, ap,
c2, rpi, c1);
Parasitic *pi_pole_residue = parasitics_->makePiPoleResidue(drvr_pin,
rf, ap,
c2, rpi, c1);
parasitics_->setIsReducedParasiticNetwork(pi_pole_residue, true);
findPolesResidues(parasitic_network, pi_pole_residue, drvr_pin, drvr_node);
return pi_pole_residue;
}
ReduceToPiPoleResidue2::~ReduceToPiPoleResidue2()
{
delete [] moments_;
}
void
ReduceToPiPoleResidue2::findPolesResidues(const Parasitic *parasitic_network,
Parasitic *pi_pole_residue,
const Pin *drvr_pin,
ParasiticNode *drvr_node)
{
moments_ = new ParasiticNodeValueMap[4];
findMoments(drvr_pin, drvr_node, 4);
PinConnectedPinIterator *pin_iter = network_->connectedPinIterator(drvr_pin);
while (pin_iter->hasNext()) {
const Pin *pin = pin_iter->next();
if (network_->isLoad(pin)) {
ParasiticNode *load_node =
parasitics_->findParasiticNode(parasitic_network, pin);
if (load_node) {
findPolesResidues(pi_pole_residue, drvr_pin, pin, load_node);
}
}
}
delete pin_iter;
}
void
ReduceToPiPoleResidue2::findMoments(const Pin *drvr_pin,
ParasiticNode *drvr_node,
int moment_count)
{
// Driver model thevenin resistance.
double rd = 0.0;
// Zero'th moments are all 1 because Vin(0)=1 and there is no
// current thru the resistors. Thus, there is no point in doing a
// pass to find the zero'th moments.
for (int moment_index = 1; moment_index < moment_count; moment_index++) {
double rd_i = findBranchCurrents(drvr_pin, drvr_node, 0, moment_index);
double rd_volt = rd_i * rd;
setMoment(drvr_node, 0.0, moment_index);
findMoments(drvr_pin, drvr_node, -rd_volt, 0, moment_index);
}
}
double
ReduceToPiPoleResidue2::findBranchCurrents(const Pin *drvr_pin,
ParasiticNode *node,
ParasiticResistor *from_res,
int moment_index)
{
visit(node);
double branch_i = 0.0;
double coupling_cap = 0.0;
ParasiticResistorSeq &resistors = resistor_map_[node];
for (ParasiticResistor *resistor : resistors) {
ParasiticNode *onode = parasitics_->otherNode(resistor, node);
// One commercial extractor creates resistors with identical from/to nodes.
if (onode != node
&& resistor != from_res
&& !isVisited(onode)
&& !isLoopResistor(resistor)) {
branch_i += findBranchCurrents(drvr_pin, onode, resistor, moment_index);
}
}
ParasiticCapacitorSeq &capacitors = capacitor_map_[node];
for (ParasiticCapacitor *capacitor : capacitors)
coupling_cap += parasitics_->value(capacitor);
double cap = parasitics_->nodeGndCap(node)
+ coupling_cap * coupling_cap_multiplier_
+ pinCapacitance(node);
branch_i += cap * moment(node, moment_index - 1);
leave(node);
if (from_res) {
setCurrent(from_res, branch_i);
debugPrint(debug_, "parasitic_reduce", 3, " res i=%.3g", branch_i);
}
return branch_i;
}
void
ReduceToPiPoleResidue2::findMoments(const Pin *drvr_pin,
ParasiticNode *node,
double from_volt,
ParasiticResistor *from_res,
int moment_index)
{
visit(node);
ParasiticResistorSeq &resistors = resistor_map_[node];
for (ParasiticResistor *resistor : resistors) {
ParasiticNode *onode = parasitics_->otherNode(resistor, node);
// One commercial extractor creates resistors with identical from/to nodes.
if (onode != node
&& resistor != from_res
&& !isVisited(onode)
&& !isLoopResistor(resistor)) {
double r = parasitics_->value(resistor);
double r_volt = r * current(resistor);
double onode_volt = from_volt - r_volt;
setMoment(onode, onode_volt, moment_index);
debugPrint(debug_, "parasitic_reduce", 3, " moment %s %d %.3g",
parasitics_->name(onode),
moment_index,
onode_volt);
findMoments(drvr_pin, onode, onode_volt, resistor, moment_index);
}
}
leave(node);
}
double
ReduceToPiPoleResidue2::moment(ParasiticNode *node,
int moment_index)
{
// Zero'th moments are all 1.
if (moment_index == 0)
return 1.0;
else {
ParasiticNodeValueMap &map = moments_[moment_index];
return map[node];
}
}
void
ReduceToPiPoleResidue2::setMoment(ParasiticNode *node,
double moment,
int moment_index)
{
// Zero'th moments are all 1.
if (moment_index > 0) {
ParasiticNodeValueMap &map = moments_[moment_index];
map[node] = moment;
}
}
double
ReduceToPiPoleResidue2::current(ParasiticResistor *res)
{
return currents_[res];
}
void
ReduceToPiPoleResidue2::setCurrent(ParasiticResistor *res,
double i)
{
currents_[res] = i;
}
void
ReduceToPiPoleResidue2::findPolesResidues(Parasitic *pi_pole_residue,
const Pin *,
const Pin *load_pin,
ParasiticNode *load_node)
{
double m1 = moment(load_node, 1);
double m2 = moment(load_node, 2);
double m3 = moment(load_node, 3);
double p1 = -m2 / m3;
double p2 = p1 * (1.0 / m1 - m1 / m2) / (m1 / m2 - m2 / m3);
if (p1 <= 0.0
|| p2 <= 0.0
// Coincident poles. Not handled by delay calculator.
|| p1 == p2
|| m1 / m2 == m2 / m3) {
double p1 = -1.0 / m1;
double k1 = 1.0;
debugPrint(debug_, "parasitic_reduce", 3, " load %s p1=%.3g k1=%.3g",
network_->pathName(load_pin), p1, k1);
ComplexFloatSeq *poles = new ComplexFloatSeq(1);
ComplexFloatSeq *residues = new ComplexFloatSeq(1);
(*poles)[0] = ComplexFloat(p1, 0.0);
(*residues)[0] = ComplexFloat(k1, 0.0);
parasitics_->setPoleResidue(pi_pole_residue, load_pin, poles, residues);
}
else {
double k1 = p1 * p1 * (1.0 + m1 * p2) / (p1 - p2);
double k2 = -p2 * p2 * (1.0 + m1 * p1) / (p1 - p2);
if (k1 < 0.0 && k2 > 0.0) {
// Swap p1 and p2.
double p = p2, k = k2;
p2 = p1;
k2 = k1;
p1 = p;
k1 = k;
}
debugPrint(debug_, "parasitic_reduce", 3,
" load %s p1=%.3g p2=%.3g k1=%.3g k2=%.3g",
network_->pathName(load_pin), p1, p2, k1, k2);
ComplexFloatSeq *poles = new ComplexFloatSeq(2);
ComplexFloatSeq *residues = new ComplexFloatSeq(2);
(*poles)[0] = ComplexFloat(p1, 0.0);
(*residues)[0] = ComplexFloat(k1, 0.0);
(*poles)[1] = ComplexFloat(p2, 0.0);
(*residues)[1] = ComplexFloat(k2, 0.0);
parasitics_->setPoleResidue(pi_pole_residue, load_pin, poles, residues);
}
}
} // namespace