From c615be4f488dce09a6f62488e8eabe1842192951 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Tue, 14 Jul 2020 15:24:47 -0700 Subject: [PATCH] create golden file for unit test and actually check it --- .gitignore | 1 + test/testcase/ispd18_sample/compare.tcl | 37 +- .../ispd18_sample/golden/ispd18_sample.log | 614 ++++++++++++++++++ 3 files changed, 642 insertions(+), 10 deletions(-) create mode 100644 test/testcase/ispd18_sample/golden/ispd18_sample.log diff --git a/.gitignore b/.gitignore index ddeac1d..e002e6c 100644 --- a/.gitignore +++ b/.gitignore @@ -4,5 +4,6 @@ build build/*.* Makefile *.log +!**/golden/*.log module/def/5.8-p029/def.output diff --git a/test/testcase/ispd18_sample/compare.tcl b/test/testcase/ispd18_sample/compare.tcl index d0dd022..e64ce82 100755 --- a/test/testcase/ispd18_sample/compare.tcl +++ b/test/testcase/ispd18_sample/compare.tcl @@ -11,19 +11,36 @@ set test_drc [format "%12d" 0] set golden_drc [format "%12d" 0] if {[file exists $golden_log]} { - catch {set golden_wirelength [format "%12d" [exec grep -e {total wire length = } $golden_log | tail -1 awk {{print $5}}]]} - catch {set golden_via [format "%12d" [exec grep -e {total number of vias = } $golden_log | tail -1 awk {{print $6}}]]} - catch {set golden_drc [format "%12d" [exec grep -e {number of violations = } $golden_log | tail -1 awk {{print $5}}]]} + set golden_wirelength [format "%12d" [exec grep -e {total wire length = } $golden_log | tail -1 | awk {{print $5}}]] + set golden_via [format "%12d" [exec grep -e {total number of vias = } $golden_log | tail -1 | awk {{print $6}}]] + set golden_drc [format "%12d" [exec grep -e {number of violations = } $golden_log | tail -1 | awk {{print $5}}]] +} else { + puts "golden file $golden_log not found" + exit 1 } if {[file exists $test_log]} { - catch {set test_wirelength [format "%12d" [exec grep -e {total wire length = } $test_log | tail -1 awk {{print $5}}]]} - catch {set test_via [format "%12d" [exec grep -e {total number of vias = } $test_log | tail -1 awk {{print $6}}]]} - catch {set test_drc [format "%12d" [exec grep -e {number of violations = } $test_log | tail -1 awk {{print $5}}]]} + set test_wirelength [format "%12d" [exec grep -e {total wire length = } $test_log | tail -1 | awk {{print $5}}]] + set test_via [format "%12d" [exec grep -e {total number of vias = } $test_log | tail -1 | awk {{print $6}}]] + set test_drc [format "%12d" [exec grep -e {number of violations = } $test_log | tail -1 | awk {{print $5}}]] +} else { + puts "test file $test_log not found" + exit 1 } -if { $golden_wirelength >= $test_wirelength && $golden_via >= $test_via && $golden_drc >= $test_drc } { - exit 0 -} else { +if { $golden_wirelength < $test_wirelength } { + puts "Wire Length: golden=$golden_wirelength test=$test_wirelength" exit 1 -} \ No newline at end of file +} + +if { $golden_via < $test_via } { + puts "Vias: golden=$golden_via test=$test_via" + exit 1 +} + +if { $golden_drc < $test_drc } { + puts "DRC: golden=$golden_drc test=$test_drc" + exit 1 +} + +exit 0 diff --git a/test/testcase/ispd18_sample/golden/ispd18_sample.log b/test/testcase/ispd18_sample/golden/ispd18_sample.log new file mode 100644 index 0000000..6cff9ad --- /dev/null +++ b/test/testcase/ispd18_sample/golden/ispd18_sample.log @@ -0,0 +1,614 @@ + +reading lef ... +USEMINSPACING OBS ON +Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule +Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH +Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule +Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH +Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule +Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH +Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule +Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH +Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule +Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH +Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule +Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH +Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule +Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH +Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule +Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH +Warning: new SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule +Warning: override minspacing rule, original type is SPACINGTABLE PARALLELRUNLENGTH, new type is SPACINGTABLE PARALLELRUNLENGTH + +units: 2000 +#layers: 19 +#macros: 16 +#vias: 22 +#viarulegen: 0 + +reading def ... + +design: ispd18_sample +die area: ( 83600 71820 ) ( 104400 91200 ) +trackPts: 18 +defvias: 0 +#components: 22 +#terminals: 0 +#snets: 0 +#nets: 11 + +reading guide ... + +#guides: 52 +Warning: Metal5 does not have viaDef align with layer direction, generating new viaDef Via5_FR... +Warning: Metal6 does not have viaDef align with layer direction, generating new viaDef Via6_FR... +Warning: Metal7 does not have viaDef align with layer direction, generating new viaDef Via7_FR... +done initConstraintLayerIdx +List of default vias: + Layer Via1 + default via: VIA12_1C + Layer Via2 + default via: VIA23_1C + Layer Via3 + default via: VIA34_1C + Layer Via4 + default via: VIA45_1C + Layer Via5 + default via: Via5_FR + Layer Via6 + default via: Via6_FR + Layer Via7 + default via: Via7_FR + Layer Via8 + default via: VIA8_0_VH +Writing reference output def... + +libcell analysis ... + +instance analysis ... +#unique instances = 17 + +init region query ... + complete FR_MASTERSLICE + complete FR_VIA + complete Metal1 + complete Via1 + complete Metal2 + complete Via2 + complete Metal3 + complete Via3 + complete Metal4 + complete Via4 + complete Metal5 + complete Via5 + complete Metal6 + complete Via6 + complete Metal7 + complete Via7 + complete Metal8 + complete Via8 + complete Metal9 + +FR_MASTERSLICE shape region query size = 0 +FR_VIA shape region query size = 0 +Metal1 shape region query size = 344 +Via1 shape region query size = 0 +Metal2 shape region query size = 0 +Via2 shape region query size = 0 +Metal3 shape region query size = 0 +Via3 shape region query size = 0 +Metal4 shape region query size = 0 +Via4 shape region query size = 0 +Metal5 shape region query size = 0 +Via5 shape region query size = 0 +Metal6 shape region query size = 0 +Via6 shape region query size = 0 +Metal7 shape region query size = 0 +Via7 shape region query size = 0 +Metal8 shape region query size = 0 +Via8 shape region query size = 0 +Metal9 shape region query size = 0 + + +start pin access + complete 79 pins + complete 17 unique inst patterns + complete 19 groups +Expt1 runtime (pin-level access point gen): 0.183736 +Expt2 runtime (design-level access pattern gen): 0.127199 +#scanned instances = 22 +#unique instances = 17 +#stdCellGenAp = 396 +#stdCellValidPlanarAp = 0 +#stdCellValidViaAp = 352 +#stdCellPinNoAp = 0 +#stdCellPinCnt = 22 +#instTermValidViaApCnt = 0 +#macroGenAp = 0 +#macroValidPlanarAp = 0 +#macroValidViaAp = 0 +#macroNoAp = 0 + +complete pin access +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4.34 (MB), peak = 4.42 (MB) + +post process guides ... +GCELLGRID X 71820 DO 3 STEP 5700 ; +GCELLGRID Y 83600 DO 3 STEP 6000 ; + complete FR_MASTERSLICE + complete FR_VIA + complete Metal1 + complete Via1 + complete Metal2 + complete Via2 + complete Metal3 + complete Via3 + complete Metal4 + complete Via4 + complete Metal5 + complete Via5 + complete Metal6 + complete Via6 + complete Metal7 + complete Via7 + complete Metal8 + complete Via8 + complete Metal9 + +building cmap ... + +init guide query ... + complete FR_MASTERSLICE (guide) + complete FR_VIA (guide) + complete Metal1 (guide) + complete Via1 (guide) + complete Metal2 (guide) + complete Via2 (guide) + complete Metal3 (guide) + complete Via3 (guide) + complete Metal4 (guide) + complete Via4 (guide) + complete Metal5 (guide) + complete Via5 (guide) + complete Metal6 (guide) + complete Via6 (guide) + complete Metal7 (guide) + complete Via7 (guide) + complete Metal8 (guide) + complete Via8 (guide) + complete Metal9 (guide) + +FR_MASTERSLICE guide region query size = 0 +FR_VIA guide region query size = 0 +Metal1 guide region query size = 22 +Via1 guide region query size = 0 +Metal2 guide region query size = 22 +Via2 guide region query size = 0 +Metal3 guide region query size = 10 +Via3 guide region query size = 0 +Metal4 guide region query size = 0 +Via4 guide region query size = 0 +Metal5 guide region query size = 0 +Via5 guide region query size = 0 +Metal6 guide region query size = 0 +Via6 guide region query size = 0 +Metal7 guide region query size = 0 +Via7 guide region query size = 0 +Metal8 guide region query size = 0 +Via8 guide region query size = 0 +Metal9 guide region query size = 0 + +init gr pin query ... +Waring: no output guide specified, skipped writing guide + + +start track assignment +Done with 22 vertical wires in 1 frboxes and 32 horizontal wires in 1 frboxes. +Done with 2 vertical wires in 1 frboxes and 1 horizontal wires in 1 frboxes. + +complete track assignment +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4.42 (MB), peak = 4.67 (MB) +Waring: no output def specified, skipped writing track assignment def + +start routing data preparation +initVia2ViaMinLen_minSpc Metal1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 380) +initVia2ViaMinLen_minSpc Metal2 (d2d, d2u, u2d, u2u) = (260, 0, 0, 280) +initVia2ViaMinLen_minSpc Metal3 (d2d, d2u, u2d, u2u) = (280, 0, 0, 280) +initVia2ViaMinLen_minSpc Metal4 (d2d, d2u, u2d, u2u) = (280, 0, 0, 280) +initVia2ViaMinLen_minSpc Metal5 (d2d, d2u, u2d, u2u) = (280, 0, 0, 280) +initVia2ViaMinLen_minSpc Metal6 (d2d, d2u, u2d, u2u) = (280, 0, 0, 1340) +initVia2ViaMinLen_minSpc Metal7 (d2d, d2u, u2d, u2u) = (1340, 1340, 1340, 1340) +initVia2ViaMinLen_minSpc Metal8 (d2d, d2u, u2d, u2u) = (1340, 1340, 1340, 1340) +initVia2ViaMinLen_minSpc Metal9 (d2d, d2u, u2d, u2u) = (1340, 0, 0, 0) +initVia2ViaMinLen_minimumcut Metal1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 380) +initVia2ViaMinLen_minimumcut Metal1 zerolen (b, b, b, b) = (1, 1, 1, 1) +initVia2ViaMinLen_minimumcut Metal2 (d2d, d2u, u2d, u2u) = (260, 0, 0, 280) +initVia2ViaMinLen_minimumcut Metal2 zerolen (b, b, b, b) = (1, 1, 1, 1) +initVia2ViaMinLen_minimumcut Metal3 (d2d, d2u, u2d, u2u) = (280, 0, 0, 280) +initVia2ViaMinLen_minimumcut Metal3 zerolen (b, b, b, b) = (1, 1, 1, 1) +initVia2ViaMinLen_minimumcut Metal4 (d2d, d2u, u2d, u2u) = (280, 0, 0, 280) +initVia2ViaMinLen_minimumcut Metal4 zerolen (b, b, b, b) = (1, 1, 1, 1) +initVia2ViaMinLen_minimumcut Metal5 (d2d, d2u, u2d, u2u) = (280, 0, 0, 280) +initVia2ViaMinLen_minimumcut Metal5 zerolen (b, b, b, b) = (1, 1, 1, 1) +initVia2ViaMinLen_minimumcut Metal6 (d2d, d2u, u2d, u2u) = (280, 0, 0, 1340) +initVia2ViaMinLen_minimumcut Metal6 zerolen (b, b, b, b) = (1, 1, 1, 1) +initVia2ViaMinLen_minimumcut Metal7 (d2d, d2u, u2d, u2u) = (1340, 1340, 1340, 1340) +initVia2ViaMinLen_minimumcut Metal7 zerolen (b, b, b, b) = (1, 1, 1, 1) +initVia2ViaMinLen_minimumcut Metal8 (d2d, d2u, u2d, u2u) = (1340, 1340, 1340, 1340) +initVia2ViaMinLen_minimumcut Metal8 zerolen (b, b, b, b) = (1, 1, 1, 1) +initVia2ViaMinLen_minimumcut Metal9 (d2d, d2u, u2d, u2u) = (1340, 0, 0, 0) +initVia2ViaMinLen_minimumcut Metal9 zerolen (b, b, b, b) = (1, 1, 1, 1) +initVia2ViaMinLenNew_minSpc Metal1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 380, 400) +initVia2ViaMinLenNew_minSpc Metal2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (380, 260, 280, 0, 280, 0, 400, 280) +initVia2ViaMinLenNew_minSpc Metal3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (280, 400, 0, 280, 0, 280, 280, 400) +initVia2ViaMinLenNew_minSpc Metal4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (400, 280, 280, 0, 280, 0, 400, 280) +initVia2ViaMinLenNew_minSpc Metal5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (280, 400, 0, 280, 0, 280, 280, 400) +initVia2ViaMinLenNew_minSpc Metal6 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (400, 280, 770, 0, 770, 0, 1340, 1340) +initVia2ViaMinLenNew_minSpc Metal7 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 1340, 1100, 1340, 1100, 1340, 1340) +initVia2ViaMinLenNew_minSpc Metal8 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 1100, 1340, 1100, 1340, 1340, 1340) +initVia2ViaMinLenNew_minSpc Metal9 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 0, 0, 0, 0, 0, 0) +initVia2ViaMinLenNew_minimumcut Metal1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 380, 400) +initVia2ViaMinLenNew_minimumcut Metal2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (380, 260, 280, 0, 280, 0, 400, 280) +initVia2ViaMinLenNew_minimumcut Metal3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (280, 400, 0, 280, 0, 280, 280, 400) +initVia2ViaMinLenNew_minimumcut Metal4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (400, 280, 280, 0, 280, 0, 400, 280) +initVia2ViaMinLenNew_minimumcut Metal5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (280, 400, 0, 280, 0, 280, 280, 400) +initVia2ViaMinLenNew_minimumcut Metal6 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (400, 280, 770, 0, 770, 0, 1340, 1340) +initVia2ViaMinLenNew_minimumcut Metal7 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 1340, 1100, 1340, 1100, 1340, 1340) +initVia2ViaMinLenNew_minimumcut Metal8 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 1100, 1340, 1100, 1340, 1340, 1340) +initVia2ViaMinLenNew_minimumcut Metal9 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 0, 0, 0, 0, 0, 0) +initVia2ViaMinLenNew_cutSpc Metal1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 380, 400) +initVia2ViaMinLenNew_cutSpc Metal2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (380, 280, 280, 0, 280, 0, 400, 280) +initVia2ViaMinLenNew_cutSpc Metal3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (280, 400, 0, 280, 0, 280, 280, 400) +initVia2ViaMinLenNew_cutSpc Metal4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (400, 280, 280, 0, 280, 0, 400, 280) +initVia2ViaMinLenNew_cutSpc Metal5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (280, 400, 0, 280, 0, 280, 280, 400) +initVia2ViaMinLenNew_cutSpc Metal6 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (400, 280, 770, 0, 770, 0, 1340, 1340) +initVia2ViaMinLenNew_cutSpc Metal7 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 1340, 1100, 1340, 1100, 1340, 1340) +initVia2ViaMinLenNew_cutSpc Metal8 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 1100, 1340, 1100, 1340, 1340, 1340) +initVia2ViaMinLenNew_cutSpc Metal9 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1340, 1340, 0, 0, 0, 0, 0, 0) +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4.67 (MB), peak = 4.71 (MB) + +start detail routing ... +start 0th optimization iteration ... + completing 10% with 0 violations + elapsed time = 00:00:00, memory = 5.73 (MB) + number of violations = 0 +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 5.88 (MB), peak = 512.85 (MB) +total wire length = 77 um +total wire length on LAYER Metal1 = 2 um +total wire length on LAYER Metal2 = 31 um +total wire length on LAYER Metal3 = 43 um +total wire length on LAYER Metal4 = 0 um +total wire length on LAYER Metal5 = 0 um +total wire length on LAYER Metal6 = 0 um +total wire length on LAYER Metal7 = 0 um +total wire length on LAYER Metal8 = 0 um +total wire length on LAYER Metal9 = 0 um +total number of vias = 44 +up-via summary (total 44): + +--------------------- + FR_MASTERSLICE 0 + Metal1 24 + Metal2 20 + Metal3 0 + Metal4 0 + Metal5 0 + Metal6 0 + Metal7 0 + Metal8 0 +--------------------- + 44 + + +start 1st optimization iteration ... + completing 10% with 0 violations + elapsed time = 00:00:00, memory = 6.39 (MB) + number of violations = 0 +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB) +total wire length = 77 um +total wire length on LAYER Metal1 = 2 um +total wire length on LAYER Metal2 = 31 um +total wire length on LAYER Metal3 = 43 um +total wire length on LAYER Metal4 = 0 um +total wire length on LAYER Metal5 = 0 um +total wire length on LAYER Metal6 = 0 um +total wire length on LAYER Metal7 = 0 um +total wire length on LAYER Metal8 = 0 um +total wire length on LAYER Metal9 = 0 um +total number of vias = 44 +up-via summary (total 44): + +--------------------- + FR_MASTERSLICE 0 + Metal1 24 + Metal2 20 + Metal3 0 + Metal4 0 + Metal5 0 + Metal6 0 + Metal7 0 + Metal8 0 +--------------------- + 44 + + +start 2nd optimization iteration ... + completing 10% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + completing 20% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + completing 30% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + completing 40% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + number of violations = 0 +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB) +total wire length = 77 um +total wire length on LAYER Metal1 = 2 um +total wire length on LAYER Metal2 = 31 um +total wire length on LAYER Metal3 = 43 um +total wire length on LAYER Metal4 = 0 um +total wire length on LAYER Metal5 = 0 um +total wire length on LAYER Metal6 = 0 um +total wire length on LAYER Metal7 = 0 um +total wire length on LAYER Metal8 = 0 um +total wire length on LAYER Metal9 = 0 um +total number of vias = 44 +up-via summary (total 44): + +--------------------- + FR_MASTERSLICE 0 + Metal1 24 + Metal2 20 + Metal3 0 + Metal4 0 + Metal5 0 + Metal6 0 + Metal7 0 + Metal8 0 +--------------------- + 44 + + +start 17th optimization iteration ... + completing 10% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + number of violations = 0 +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB) +total wire length = 77 um +total wire length on LAYER Metal1 = 2 um +total wire length on LAYER Metal2 = 31 um +total wire length on LAYER Metal3 = 43 um +total wire length on LAYER Metal4 = 0 um +total wire length on LAYER Metal5 = 0 um +total wire length on LAYER Metal6 = 0 um +total wire length on LAYER Metal7 = 0 um +total wire length on LAYER Metal8 = 0 um +total wire length on LAYER Metal9 = 0 um +total number of vias = 44 +up-via summary (total 44): + +--------------------- + FR_MASTERSLICE 0 + Metal1 24 + Metal2 20 + Metal3 0 + Metal4 0 + Metal5 0 + Metal6 0 + Metal7 0 + Metal8 0 +--------------------- + 44 + + +start 25th optimization iteration ... + completing 10% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + number of violations = 0 +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB) +total wire length = 77 um +total wire length on LAYER Metal1 = 2 um +total wire length on LAYER Metal2 = 31 um +total wire length on LAYER Metal3 = 43 um +total wire length on LAYER Metal4 = 0 um +total wire length on LAYER Metal5 = 0 um +total wire length on LAYER Metal6 = 0 um +total wire length on LAYER Metal7 = 0 um +total wire length on LAYER Metal8 = 0 um +total wire length on LAYER Metal9 = 0 um +total number of vias = 44 +up-via summary (total 44): + +--------------------- + FR_MASTERSLICE 0 + Metal1 24 + Metal2 20 + Metal3 0 + Metal4 0 + Metal5 0 + Metal6 0 + Metal7 0 + Metal8 0 +--------------------- + 44 + + +start 33rd optimization iteration ... + completing 10% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + completing 20% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + completing 30% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + completing 40% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + number of violations = 0 +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB) +total wire length = 77 um +total wire length on LAYER Metal1 = 2 um +total wire length on LAYER Metal2 = 31 um +total wire length on LAYER Metal3 = 43 um +total wire length on LAYER Metal4 = 0 um +total wire length on LAYER Metal5 = 0 um +total wire length on LAYER Metal6 = 0 um +total wire length on LAYER Metal7 = 0 um +total wire length on LAYER Metal8 = 0 um +total wire length on LAYER Metal9 = 0 um +total number of vias = 44 +up-via summary (total 44): + +--------------------- + FR_MASTERSLICE 0 + Metal1 24 + Metal2 20 + Metal3 0 + Metal4 0 + Metal5 0 + Metal6 0 + Metal7 0 + Metal8 0 +--------------------- + 44 + + +start 41st optimization iteration ... + completing 10% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + completing 20% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + completing 30% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + completing 40% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + number of violations = 0 +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB) +total wire length = 77 um +total wire length on LAYER Metal1 = 2 um +total wire length on LAYER Metal2 = 31 um +total wire length on LAYER Metal3 = 43 um +total wire length on LAYER Metal4 = 0 um +total wire length on LAYER Metal5 = 0 um +total wire length on LAYER Metal6 = 0 um +total wire length on LAYER Metal7 = 0 um +total wire length on LAYER Metal8 = 0 um +total wire length on LAYER Metal9 = 0 um +total number of vias = 44 +up-via summary (total 44): + +--------------------- + FR_MASTERSLICE 0 + Metal1 24 + Metal2 20 + Metal3 0 + Metal4 0 + Metal5 0 + Metal6 0 + Metal7 0 + Metal8 0 +--------------------- + 44 + + +start 49th optimization iteration ... + completing 10% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + number of violations = 0 +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB) +total wire length = 77 um +total wire length on LAYER Metal1 = 2 um +total wire length on LAYER Metal2 = 31 um +total wire length on LAYER Metal3 = 43 um +total wire length on LAYER Metal4 = 0 um +total wire length on LAYER Metal5 = 0 um +total wire length on LAYER Metal6 = 0 um +total wire length on LAYER Metal7 = 0 um +total wire length on LAYER Metal8 = 0 um +total wire length on LAYER Metal9 = 0 um +total number of vias = 44 +up-via summary (total 44): + +--------------------- + FR_MASTERSLICE 0 + Metal1 24 + Metal2 20 + Metal3 0 + Metal4 0 + Metal5 0 + Metal6 0 + Metal7 0 + Metal8 0 +--------------------- + 44 + + +start 57th optimization iteration ... + completing 10% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + completing 20% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + completing 30% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + completing 40% with 0 violations + elapsed time = 00:00:00, memory = 12.34 (MB) + number of violations = 0 +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB) +total wire length = 77 um +total wire length on LAYER Metal1 = 2 um +total wire length on LAYER Metal2 = 31 um +total wire length on LAYER Metal3 = 43 um +total wire length on LAYER Metal4 = 0 um +total wire length on LAYER Metal5 = 0 um +total wire length on LAYER Metal6 = 0 um +total wire length on LAYER Metal7 = 0 um +total wire length on LAYER Metal8 = 0 um +total wire length on LAYER Metal9 = 0 um +total number of vias = 44 +up-via summary (total 44): + +--------------------- + FR_MASTERSLICE 0 + Metal1 24 + Metal2 20 + Metal3 0 + Metal4 0 + Metal5 0 + Metal6 0 + Metal7 0 + Metal8 0 +--------------------- + 44 + + +complete detail routing +total wire length = 77 um +total wire length on LAYER Metal1 = 2 um +total wire length on LAYER Metal2 = 31 um +total wire length on LAYER Metal3 = 43 um +total wire length on LAYER Metal4 = 0 um +total wire length on LAYER Metal5 = 0 um +total wire length on LAYER Metal6 = 0 um +total wire length on LAYER Metal7 = 0 um +total wire length on LAYER Metal8 = 0 um +total wire length on LAYER Metal9 = 0 um +total number of vias = 44 +up-via summary (total 44): + +--------------------- + FR_MASTERSLICE 0 + Metal1 24 + Metal2 20 + Metal3 0 + Metal4 0 + Metal5 0 + Metal6 0 + Metal7 0 + Metal8 0 +--------------------- + 44 + +cpu time = 00:00:00, elapsed time = 00:00:00, memory = 12.34 (MB), peak = 512.85 (MB) + +post processing ... + +Runtime taken (hrt): 1.23143