mirror of
https://github.com/The-OpenROAD-Project/abc.git
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291 lines
8.6 KiB
C
291 lines
8.6 KiB
C
/**CFile****************************************************************
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FileName [fraSec.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [New FRAIG package.]
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Synopsis [Performs SEC based on seq sweeping.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 30, 2007.]
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Revision [$Id: fraSec.c,v 1.00 2007/06/30 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "fra.h"
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#include "ioa.h"
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Fra_FraigSec2( Aig_Man_t * p, int nFramesFix, int fVerbose, int fVeryVerbose )
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{
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Aig_Man_t * pNew;
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int nFrames, RetValue, nIter, clk, clkTotal = clock();
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int fLatchCorr = 0;
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if ( nFramesFix )
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{
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nFrames = nFramesFix;
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// perform seq sweeping for one frame number
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pNew = Fra_FraigInduction( p, 0, nFrames, 0, 0, 0, 0, fLatchCorr, 0, 0, fVeryVerbose, &nIter );
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}
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else
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{
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// perform seq sweeping while increasing the number of frames
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for ( nFrames = 1; ; nFrames++ )
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{
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clk = clock();
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pNew = Fra_FraigInduction( p, 0, nFrames, 0, 0, 0, 0, fLatchCorr, 0, 0, fVeryVerbose, &nIter );
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RetValue = Fra_FraigMiterStatus( pNew );
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if ( fVerbose )
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{
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printf( "FRAMES %3d : Iters = %3d. ", nFrames, nIter );
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if ( RetValue == 1 )
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printf( "UNSAT " );
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else
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printf( "UNDECIDED " );
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PRT( "Time", clock() - clk );
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}
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if ( RetValue != -1 )
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break;
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Aig_ManStop( pNew );
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}
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}
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// get the miter status
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RetValue = Fra_FraigMiterStatus( pNew );
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Aig_ManStop( pNew );
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// report the miter
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if ( RetValue == 1 )
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printf( "Networks are equivalent after seq sweeping with K=%d frames (%d iters). ", nFrames, nIter );
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else if ( RetValue == 0 )
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printf( "Networks are NOT EQUIVALENT. " );
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else
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printf( "Networks are UNDECIDED after seq sweeping with K=%d frames (%d iters). ", nFrames, nIter );
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PRT( "Time", clock() - clkTotal );
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return RetValue;
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Fra_FraigSec( Aig_Man_t * p, int nFramesMax, int fRetimeFirst, int fVerbose, int fVeryVerbose )
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{
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Fra_Sml_t * pSml;
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Aig_Man_t * pNew, * pTemp;
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int nFrames, RetValue, nIter, clk, clkTotal = clock();
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int fLatchCorr = 0;
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pNew = Aig_ManDup( p, 1 );
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if ( fVerbose )
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{
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printf( "Original miter: Latches = %5d. Nodes = %6d.\n",
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Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
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}
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//Aig_ManDumpBlif( pNew, "after.blif" );
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// perform sequential cleanup
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clk = clock();
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if ( pNew->nRegs )
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pNew = Aig_ManReduceLaches( pNew, 0 );
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if ( pNew->nRegs )
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pNew = Aig_ManConstReduce( pNew, 0 );
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if ( fVerbose )
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{
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printf( "Sequential cleanup: Latches = %5d. Nodes = %6d. ",
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Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
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PRT( "Time", clock() - clk );
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}
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// perform forward retiming
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if ( fRetimeFirst && pNew->nRegs )
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{
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clk = clock();
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pNew = Rtm_ManRetime( pTemp = pNew, 1, 1000, 0 );
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Aig_ManStop( pTemp );
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if ( fVerbose )
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{
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printf( "Forward retiming: Latches = %5d. Nodes = %6d. ",
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Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
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PRT( "Time", clock() - clk );
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}
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}
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// run latch correspondence
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clk = clock();
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if ( pNew->nRegs )
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{
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pNew = Aig_ManDup( pTemp = pNew, 1 );
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Aig_ManStop( pTemp );
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pNew = Fra_FraigLatchCorrespondence( pTemp = pNew, 0, 100000, 1, fVeryVerbose, &nIter );
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p->pSeqModel = pTemp->pSeqModel; pTemp->pSeqModel = NULL;
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Aig_ManStop( pTemp );
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if ( pNew == NULL )
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{
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RetValue = 0;
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printf( "Networks are NOT EQUIVALENT after simulation. " );
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PRT( "Time", clock() - clkTotal );
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return RetValue;
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}
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if ( fVerbose )
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{
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printf( "Latch-corr (I=%3d): Latches = %5d. Nodes = %6d. ",
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nIter, Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
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PRT( "Time", clock() - clk );
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}
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}
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// perform fraiging
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clk = clock();
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pNew = Fra_FraigEquivence( pTemp = pNew, 100, 0 );
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Aig_ManStop( pTemp );
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if ( fVerbose )
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{
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printf( "Fraiging: Latches = %5d. Nodes = %6d. ",
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Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
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PRT( "Time", clock() - clk );
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}
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// perform seq sweeping while increasing the number of frames
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RetValue = Fra_FraigMiterStatus( pNew );
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if ( RetValue == -1 )
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for ( nFrames = 1; nFrames <= nFramesMax; nFrames *= 2 )
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{
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clk = clock();
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pNew = Fra_FraigInduction( pTemp = pNew, 0, nFrames, 0, 0, 0, 0, fLatchCorr, 0, 0, fVeryVerbose, &nIter );
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Aig_ManStop( pTemp );
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RetValue = Fra_FraigMiterStatus( pNew );
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if ( fVerbose )
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{
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printf( "K-step (K=%2d,I=%3d): Latches = %5d. Nodes = %6d. ",
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nFrames, nIter, Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
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PRT( "Time", clock() - clk );
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}
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if ( RetValue != -1 )
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break;
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// perform rewriting
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clk = clock();
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pNew = Aig_ManDup( pTemp = pNew, 1 );
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Aig_ManStop( pTemp );
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pNew = Dar_ManRewriteDefault( pTemp = pNew );
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Aig_ManStop( pTemp );
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if ( fVerbose )
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{
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printf( "Rewriting: Latches = %5d. Nodes = %6d. ",
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Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
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PRT( "Time", clock() - clk );
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}
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// perform retiming
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if ( fRetimeFirst && pNew->nRegs )
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// if ( pNew->nRegs )
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{
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clk = clock();
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pNew = Rtm_ManRetime( pTemp = pNew, 1, 1000, 0 );
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Aig_ManStop( pTemp );
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pNew = Aig_ManDup( pTemp = pNew, 1 );
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Aig_ManStop( pTemp );
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if ( fVerbose )
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{
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printf( "Forward retiming: Latches = %5d. Nodes = %6d. ",
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Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
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PRT( "Time", clock() - clk );
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}
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}
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if ( pNew->nRegs )
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pNew = Aig_ManConstReduce( pNew, 0 );
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// perform sequential simulation
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if ( pNew->nRegs )
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{
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clk = clock();
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pSml = Fra_SmlSimulateSeq( pNew, 0, 128 * nFrames, 1 + 16/(1+Aig_ManNodeNum(pNew)/1000) );
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if ( fVerbose )
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{
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printf( "Seq simulation : Latches = %5d. Nodes = %6d. ",
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Aig_ManRegNum(pNew), Aig_ManNodeNum(pNew) );
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PRT( "Time", clock() - clk );
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}
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if ( pSml->fNonConstOut )
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{
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p->pSeqModel = Fra_SmlGetCounterExample( pSml );
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Fra_SmlStop( pSml );
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Aig_ManStop( pNew );
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RetValue = 0;
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printf( "Networks are NOT EQUIVALENT after simulation. " );
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PRT( "Time", clock() - clkTotal );
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return RetValue;
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}
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Fra_SmlStop( pSml );
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}
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}
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// get the miter status
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RetValue = Fra_FraigMiterStatus( pNew );
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// report the miter
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if ( RetValue == 1 )
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{
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printf( "Networks are equivalent. " );
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PRT( "Time", clock() - clkTotal );
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}
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else if ( RetValue == 0 )
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{
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printf( "Networks are NOT EQUIVALENT. " );
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PRT( "Time", clock() - clkTotal );
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}
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else
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{
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static int Counter = 1;
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char pFileName[1000];
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printf( "Networks are UNDECIDED. " );
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PRT( "Time", clock() - clkTotal );
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sprintf( pFileName, "sm%03d.aig", Counter++ );
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Ioa_WriteAiger( pNew, pFileName, 0, 0 );
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printf( "The unsolved reduced miter is written into file \"%s\".\n", pFileName );
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}
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Aig_ManStop( pNew );
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return RetValue;
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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