From d5d61ae2fc651a5b1c800aa48763aba73da808c6 Mon Sep 17 00:00:00 2001 From: coolsnowwolf Date: Fri, 17 Oct 2025 14:29:46 +0800 Subject: [PATCH] rockchip: refresh 6.x patches --- ...8-phy-rockchip-naneng-combphy-add-support-rk3528.patch | 8 -------- .../997-rockchip-naneng-combo-phy-add-sgmii-mac-sel.patch | 8 ++++---- ...8-phy-rockchip-naneng-combphy-add-support-rk3528.patch | 8 -------- 3 files changed, 4 insertions(+), 20 deletions(-) diff --git a/target/linux/rockchip/patches-6.12/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch b/target/linux/rockchip/patches-6.12/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch index 0bb64550b..85fcfcbd7 100644 --- a/target/linux/rockchip/patches-6.12/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch +++ b/target/linux/rockchip/patches-6.12/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch @@ -28,14 +28,6 @@ Signed-off-by: Jianwei Zheng u16 bitend; u16 bitstart; u16 disable; -@@ -107,6 +107,7 @@ struct combphy_reg { - struct rockchip_combphy_grfcfg { - struct combphy_reg pcie_mode_set; - struct combphy_reg usb_mode_set; -+ struct combphy_reg u3otg0_port_en; - struct combphy_reg sgmii_mode_set; - struct combphy_reg qsgmii_mode_set; - struct combphy_reg pipe_rxterm_set; @@ -396,6 +397,120 @@ static int rockchip_combphy_probe(struct return PTR_ERR_OR_ZERO(phy_provider); } diff --git a/target/linux/rockchip/patches-6.12/997-rockchip-naneng-combo-phy-add-sgmii-mac-sel.patch b/target/linux/rockchip/patches-6.12/997-rockchip-naneng-combo-phy-add-sgmii-mac-sel.patch index be0da4fd8..3df81b2b6 100644 --- a/target/linux/rockchip/patches-6.12/997-rockchip-naneng-combo-phy-add-sgmii-mac-sel.patch +++ b/target/linux/rockchip/patches-6.12/997-rockchip-naneng-combo-phy-add-sgmii-mac-sel.patch @@ -5,9 +5,9 @@ struct combphy_reg pipe_pcie1l0_sel; struct combphy_reg pipe_pcie1l1_sel; + struct combphy_reg pipe_sgmii_mac_sel; + struct combphy_reg u3otg0_port_en; + struct combphy_reg u3otg1_port_en; }; - - struct rockchip_combphy_cfg { @@ -290,6 +291,7 @@ static struct phy *rockchip_combphy_xlat static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv) @@ -33,6 +33,6 @@ .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, + .pipe_sgmii_mac_sel = { 0x0040, 1, 1, 0x00, 0x01 }, + .u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 }, + .u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 }, }; - - static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { diff --git a/target/linux/rockchip/patches-6.6/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch b/target/linux/rockchip/patches-6.6/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch index 8aca368f3..30f961250 100644 --- a/target/linux/rockchip/patches-6.6/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch +++ b/target/linux/rockchip/patches-6.6/308-phy-rockchip-naneng-combphy-add-support-rk3528.patch @@ -28,14 +28,6 @@ Signed-off-by: Jianwei Zheng u16 bitend; u16 bitstart; u16 disable; -@@ -107,6 +107,7 @@ struct combphy_reg { - struct rockchip_combphy_grfcfg { - struct combphy_reg pcie_mode_set; - struct combphy_reg usb_mode_set; -+ struct combphy_reg u3otg0_port_en; - struct combphy_reg sgmii_mode_set; - struct combphy_reg qsgmii_mode_set; - struct combphy_reg pipe_rxterm_set; @@ -393,6 +394,120 @@ static int rockchip_combphy_probe(struct return PTR_ERR_OR_ZERO(phy_provider); }