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OpenFPGA/.gitmodules
2026-05-09 21:43:59 -07:00

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[submodule "yosys"]
path = yosys
url = https://github.com/YosysHQ/yosys
[submodule "vtr-verilog-to-routing"]
path = vtr-verilog-to-routing
url = https://github.com/verilog-to-routing/vtr-verilog-to-routing.git
[submodule "yosys-slang"]
path = yosys-slang
url = https://github.com/povik/yosys-slang.git