Files
iverilog/PGate.cc
Lars-Peter Clausen 85c58d0a7a Use helper types for drive strengths and delays
Drive strengths and delays are often handled as a pair of drive values
and a rise/fall/decay triple. Add small helper types to carry these
groups and use them in the continuous assignment and gate/UDP elaboration
paths.

Use the same helper types when propagating drive and delay values through
netlist links.

Also add helpers for dumping the values in debug output. This keeps the
behavior consistent and fixes one small bug where some of the debug
dumps printed the pointer value for the delays, rather than the actual
delay values.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-17 14:27:45 -07:00

286 lines
5.6 KiB
C++

/*
* Copyright (c) 1999-2026 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
# include "config.h"
# include "PGate.h"
# include "PExpr.h"
# include "verinum.h"
# include "ivl_assert.h"
using namespace std;
void PGate::set_pins_(list<PExpr*>*pins)
{
ivl_assert(*this, pins);
ivl_assert(*this, pins->size() == pins_.size());
for (size_t idx = 0 ; idx < pins_.size() ; idx += 1) {
pins_[idx] = pins->front();
pins->pop_front();
}
ivl_assert(*this, pins->empty());
delete pins;
}
PGate::PGate(perm_string name, list<PExpr*>*pins, const list<PExpr*>*del)
: name_(name), pins_(pins? pins->size() : 0), ranges_(nullptr)
{
if (pins) set_pins_(pins);
if (del) delay_.set_delays(del);
}
PGate::PGate(perm_string name, list<PExpr*>*pins, PExpr*del)
: name_(name), pins_(pins? pins->size() : 0), ranges_(nullptr)
{
if (pins) set_pins_(pins);
if (del) delay_.set_delay(del);
}
PGate::PGate(perm_string name, list<PExpr*>*pins)
: name_(name), pins_(pins? pins->size() : 0), ranges_(nullptr)
{
if (pins) set_pins_(pins);
}
PGate::~PGate()
{
}
void PGate::set_ranges(list<pform_range_t>*ranges)
{
ivl_assert(*this, ranges_ == 0);
ranges_ = ranges;
}
drive_strength_t PGate::strength() const
{
return strength_;
}
void PGate::strength(const drive_strength_t &str)
{
strength_ = str;
}
void PGate::elaborate_scope(Design*, NetScope*) const
{
}
/*
* This method is used during elaboration to calculate the
* rise/fall/decay times for the gate. These values were set in pform
* by the constructor, so here I evaluate the expression in the given
* design context and save the calculated delays into the output
* parameters. This method understands how to handle the different
* numbers of expressions.
*/
void PGate::eval_delays(Design*des, NetScope*scope, delay_exprs_t &delays,
bool as_net_flag) const
{
delay_.eval_delays(des, scope, delays, as_net_flag);
}
unsigned PGate::delay_count() const
{
return delay_.delay_count();
}
PNamedItem::SymbolType PGate::symbol_type() const
{
return INSTANCE;
}
PGAssign::PGAssign(list<PExpr*>*pins)
: PGate(perm_string(), pins)
{
ivl_assert(*this, pin_count() == 2);
}
PGAssign::PGAssign(list<PExpr*>*pins, list<PExpr*>*dels)
: PGate(perm_string(), pins, dels)
{
ivl_assert(*this, pin_count() == 2);
}
PGAssign::~PGAssign()
{
}
PGBuiltin::PGBuiltin(Type t, perm_string name,
list<PExpr*>*pins,
const list<PExpr*>*del)
: PGate(name, pins, del), type_(t)
{
}
PGBuiltin::PGBuiltin(Type t, perm_string name,
list<PExpr*>*pins,
PExpr*del)
: PGate(name, pins, del), type_(t)
{
}
PGBuiltin::~PGBuiltin()
{
}
const char* PGBuiltin::gate_name() const
{
switch(type_) {
case AND:
return "AND";
break;
case NAND:
return "NAND";
break;
case OR:
return "OR";
break;
case NOR:
return "NOR";
break;
case XOR:
return "XOR";
break;
case XNOR:
return "XNOR";
break;
case BUF:
return "BUF";
break;
case NOT:
return "NOT";
break;
case BUFIF0:
return "BUFIF0";
break;
case NOTIF0:
return "NOTIF0";
break;
case BUFIF1:
return "BUFIF1";
break;
case NOTIF1:
return "NOTIF1";
break;
case NMOS:
return "NMOS";
break;
case RNMOS:
return "RNMOS";
break;
case PMOS:
return "PMOS";
break;
case RPMOS:
return "RPMOS";
break;
case TRAN:
return "TRAN";
break;
case RTRAN:
return "RTRAN";
break;
case TRANIF0:
return "TRANIF0";
break;
case RTRANIF0:
return "RTRANIF0";
break;
case TRANIF1:
return "TRANIF1";
break;
case RTRANIF1:
return "RTRANIF1";
break;
case CMOS:
return "CMOS";
break;
case RCMOS:
return "RCMOS";
break;
case PULLUP:
return "PULLUP";
break;
case PULLDOWN:
return "PULLDOWN";
break;
}
return "<unknown>";
}
PGModule::PGModule(perm_string type, perm_string name, list<PExpr*>*pins)
: PGate(name, pins), bound_type_(0), type_(type), overrides_(0), pins_(0),
npins_(0), parms_(0), nparms_(0)
{
}
PGModule::PGModule(perm_string type, perm_string name,
named_pexpr_t *pins, unsigned npins)
: PGate(name, 0), bound_type_(0), type_(type), overrides_(0), pins_(pins),
npins_(npins), parms_(0), nparms_(0)
{
}
PGModule::PGModule(Module*type, perm_string name)
: PGate(name, 0), bound_type_(type), overrides_(0), pins_(0),
npins_(0), parms_(0), nparms_(0)
{
}
PGModule::~PGModule()
{
}
void PGModule::set_parameters(list<PExpr*>*o)
{
ivl_assert(*this, overrides_ == 0);
overrides_ = o;
}
void PGModule::set_parameters(named_pexpr_t *pa, unsigned npa)
{
ivl_assert(*this, parms_ == 0);
ivl_assert(*this, overrides_ == 0);
parms_ = pa;
nparms_ = npa;
}
perm_string PGModule::get_type() const
{
return type_;
}