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SystemVerilog requires that functions and tasks are not implicitly imported if a symbol with the same name appears in the scope, even if it the symbol is declared after its usage. To support this a list of potential imports is collected while parsing a scope and only when the end of the scope is reached it is evaluated whether the symbol should be imported or not based on whether it already exists in the scope. This currently works fine for all scopes except for the unit scope. Since the unit scope might span multiple files it is never explicitly closed and the potential imports are never checked. Make sure that after parsing all files is done the potential imports for the unit scope are checked. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
71 lines
2.4 KiB
C++
71 lines
2.4 KiB
C++
#ifndef IVL_parse_api_H
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#define IVL_parse_api_H
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/*
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* Copyright (c) 2001-2021 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# include <cstdio>
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# include "StringHeap.h"
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# include <string>
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# include <ostream>
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# include <map>
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# include <set>
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class Design;
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class Module;
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class PClass;
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class PPackage;
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class PTaskFunc;
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class PUdp;
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class data_type_t;
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struct enum_type_t;
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/*
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* These are maps of the modules and primitives parsed from the
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* Verilog source into pform for elaboration. The parser adds modules
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* to these maps as it compiles modules in the Verilog source.
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*/
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extern std::map<perm_string,Module*> pform_modules;
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extern std::map<perm_string,PUdp*> pform_primitives;
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extern std::vector<PPackage*> pform_units;
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extern std::vector<PPackage*> pform_packages;
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extern void pform_dump(std::ostream&out, const PClass*pac);
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extern void pform_dump(std::ostream&out, const PPackage*pac);
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extern void pform_dump(std::ostream&out, const PTaskFunc*tf);
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/*
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* This code actually invokes the parser to make modules. If the path
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* parameter is "-", the parser reads from stdin, otherwise it attempts
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* to open and read the specified file. When reading from a file, if
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* the ivlpp_string variable is not set to null, the file will be piped
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* through the command specified by ivlpp_string before being parsed.
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*/
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extern int pform_parse(const char*path);
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extern void pform_finish();
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extern std::string vl_file;
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extern void pform_set_timescale(int units, int prec, const char*file,
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unsigned lineno);
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extern int def_ts_units;
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extern int def_ts_prec;
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#endif /* IVL_parse_api_H */
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