KestrelComputer/polaris
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  • 764f849170 Merge pull request #27 from olofk/bootrom_fix master Samuel A. Falvo II 2016-12-12 22:18:43 -08:00
  • 1ca74807bd Merge pull request #28 from sam-falvo/master Samuel A. Falvo II 2016-12-12 22:17:02 -08:00
  • 94e91866dd Add 64-bit writes Samuel A. Falvo II 2016-12-12 22:14:21 -08:00
  • 7adb7f9b93 64-bit read support Samuel A. Falvo II 2016-12-12 21:41:49 -08:00
  • aad7290dd3 Rework core to use SMG. Supports 32-bit transfers. Samuel A. Falvo II 2016-12-12 20:46:38 -08:00
  • 09a2013b26 Start of 32-bit read support. Samuel A. Falvo II 2016-12-12 01:04:19 -08:00
  • 6e9c009250 Make boot ROM contents configurable through top-level parameter Olof Kindgren 2016-12-12 08:38:42 +01:00
  • e88b7fbda4 Merge pull request #26 from sam-falvo/master Samuel A. Falvo II 2016-12-12 00:38:35 -08:00
  • e2d587bd64 Add 16-bit write support Samuel A. Falvo II 2016-12-11 22:30:22 -08:00
  • 88dcdf1547 Add 16-bit reads Samuel A. Falvo II 2016-12-11 22:19:20 -08:00
  • f6eb09db6b Support 8-bit writes Samuel A. Falvo II 2016-12-11 22:01:24 -08:00
  • dca6c3f5b1 First bits of bottleneck core Samuel A. Falvo II 2016-12-11 21:35:10 -08:00
  • a06ecaff7c Fix documentation link. I hope. Samuel A. Falvo II 2016-12-11 17:26:53 -08:00
  • 7c69f06461 Complete new directory layout. Samuel A. Falvo II 2016-12-11 17:21:15 -08:00
  • d27a7ccd28 Remove unused and misleading file. Samuel A. Falvo II 2016-12-11 17:07:07 -08:00
  • 4b6f7cd5e1 Reorganize: CPU into family subdirectory Samuel A. Falvo II 2016-12-11 17:06:38 -08:00
  • 70b28aa3e4 Add Wishbone bus bridge as official core. Samuel A. Falvo II 2016-12-11 17:02:08 -08:00
  • 8ec4548b2a Make the arbiter an official core Samuel A. Falvo II 2016-12-11 16:59:47 -08:00
  • 46d0370a5e Merge pull request #23 from sam-falvo/master Samuel A. Falvo II 2016-11-26 08:32:29 -08:00
  • bf4343932a Attempt to fix formatting on Github Samuel A. Falvo II 2016-11-26 08:30:37 -08:00
  • 8cd1b2de30 Attempt to fix layout issues in Github Samuel A. Falvo II 2016-11-26 08:25:58 -08:00
  • 89f8e9e0d8 Merge pull request #22 from sam-falvo/master Samuel A. Falvo II 2016-11-26 08:15:08 -08:00
  • 035cc5321b Support SLT/SLTU instructions. Samuel A. Falvo II 2016-11-26 08:12:49 -08:00
  • 1e75ac3aeb Merge pull request #21 from sam-falvo/master Samuel A. Falvo II 2016-11-25 21:06:09 -08:00
  • 343cfe74f4 Update databook docs Samuel A. Falvo II 2016-11-25 21:02:09 -08:00
  • 6d018440a0 Modernize examples Samuel A. Falvo II 2016-11-25 16:20:45 -08:00
  • dc466751e0 Include build instructions Samuel A. Falvo II 2016-11-25 16:03:05 -08:00
  • cf4c27971f Insert Wishbone bus bridge; make ROM 64 bits. Samuel A. Falvo II 2016-11-25 15:54:46 -08:00
  • a381f8eaa8 Reset event counters to 0 on reset Samuel A. Falvo II 2016-11-25 15:52:58 -08:00
  • ec4c1ec0ff Initial WB bridge. Samuel A. Falvo II 2016-11-25 14:32:36 -08:00
  • dae061f0c0 Add bus arbiter to the example circuit. Samuel A. Falvo II 2016-11-23 20:02:25 -08:00
  • 79ddbbddd9 Merge branch 'master' of github.com:kestrelcomputer/polaris Samuel A. Falvo II 2016-11-12 16:03:16 -08:00
  • 2ecd9da14e Merge pull request #20 from sam-falvo/verilator Samuel A. Falvo II 2016-11-12 16:02:28 -08:00
  • 74b1d49221 Remove unnecessary files Samuel A. Falvo II 2016-11-12 15:58:53 -08:00
  • 7912df0f27 Remove unnecessary files Samuel A. Falvo II 2016-11-12 15:58:30 -08:00
  • a5c85cd343 Initial example computer reading from ROM. Samuel A. Falvo II 2016-11-11 23:43:41 -08:00
  • 2e5b5894bc Fix verilator UNOPTFLAT warning. Samuel A. Falvo II 2016-11-11 21:57:35 -08:00
  • 01d152118a Fix verilator warning Samuel A. Falvo II 2016-11-11 20:25:54 -08:00
  • 497a63e3cd Fix verilator warning Samuel A. Falvo II 2016-11-11 20:24:26 -08:00
  • ca80b0643d Forgot about the bench test changes. Samuel A. Falvo II 2016-11-11 20:22:30 -08:00
  • 0840bf7e0d Fixes verilator warning; however, see issue #18. Samuel A. Falvo II 2016-11-11 20:21:42 -08:00
  • bebd8fb4db Fixes warning from verilator. Samuel A. Falvo II 2016-11-11 20:19:46 -08:00
  • 1b79eabb6d WIP for debugging effort Samuel A. Falvo II 2016-11-06 22:40:57 -08:00
  • 9b564315a5 Clean up Verilog source to compile in Webpack ISE Samuel A. Falvo II 2016-11-06 22:12:07 -08:00
  • c79d737cbb Fix slli off-by-1 bug in example code. Samuel A. Falvo II 2016-11-06 10:24:58 -08:00
  • 91b80a7786 Documentation for example application Samuel A. Falvo II 2016-11-06 07:52:08 -08:00
  • 03b62f3711 BUG: iverilog deadlocks after only 300-ish clock cycles. Samuel A. Falvo II 2016-11-06 07:48:48 -08:00
  • 74596bdc16 Merge pull request #16 from sam-falvo/master Samuel A. Falvo II 2016-11-05 00:22:44 -07:00
  • b0880f24cc Use EBREAK to ensure IRQs have priority over traps Samuel A. Falvo II 2016-11-05 00:11:31 -07:00
  • a2d01fa35f IRQs implemented. Samuel A. Falvo II 2016-11-04 23:22:28 -07:00
  • 428dd87b3f Add IRQ support Samuel A. Falvo II 2016-11-04 21:28:01 -07:00
  • e89a7df017 Failing test fails as expected. Samuel A. Falvo II 2016-11-01 18:26:42 -07:00
  • 00fe677727 WIP Adding external IRQ support. Samuel A. Falvo II 2016-11-01 18:17:51 -07:00
  • be040ca9e5 Merge pull request #9 from sam-falvo/master Samuel A. Falvo II 2016-11-01 15:27:12 -07:00
  • 38982bbe84 Complete 1st draft of ISA docs Samuel A. Falvo II 2016-10-31 13:56:40 -07:00
  • 097ad3f28f CSR instructions documented Samuel A. Falvo II 2016-10-31 10:57:17 -07:00
  • 5653c38207 Flesh out the instruction set chapter. Samuel A. Falvo II 2016-10-30 22:24:34 -07:00
  • dfe0c7aa16 Small adjustments Samuel A. Falvo II 2016-10-16 19:05:43 -07:00
  • 851d341323 Going to add instruction set summary Samuel A. Falvo II 2016-10-16 18:24:23 -07:00
  • 3af19fad7c Fix some typos Samuel A. Falvo II 2016-10-16 18:16:44 -07:00
  • 66074932e4 Removed all layers except 1; still does not work Samuel A. Falvo II 2016-10-16 18:05:08 -07:00
  • c32e751cb0 Provide CSR docs Samuel A. Falvo II 2016-10-16 17:47:01 -07:00
  • 320cc84d8b Forgot notes Samuel A. Falvo II 2016-10-15 21:52:32 -07:00
  • ef8113030c Forgot notes references in diagram Samuel A. Falvo II 2016-10-15 21:50:55 -07:00
  • 9b0151eb31 Forgot signal diagram. Samuel A. Falvo II 2016-10-15 21:42:41 -07:00
  • d1249b7c7b Bus signal descriptions and timing diagrams. Samuel A. Falvo II 2016-10-15 21:17:40 -07:00
  • e9092e6713 Forgot glossary Samuel A. Falvo II 2016-10-10 09:51:29 -07:00
  • a0ce249d4e Add programming model section Samuel A. Falvo II 2016-10-10 09:51:14 -07:00
  • 03abb6f276 Add block diagram to docs Samuel A. Falvo II 2016-10-09 23:03:07 -07:00
  • cdd153b50e Writing data sheet. Samuel A. Falvo II 2016-10-09 00:25:33 -07:00
  • 84ebeee625 Merge pull request #5 from sam-falvo/master Samuel A. Falvo II 2016-10-08 16:13:47 -07:00
  • 8f3d10366b Change ISIZ_O to ISTB_O. Samuel A. Falvo II 2016-10-08 16:12:02 -07:00
  • f6fbad2d92 Internalize mtvec configuration Samuel A. Falvo II 2016-10-08 11:52:40 -07:00
  • 70bcd27558 Merge pull request #2 from sam-falvo/master Samuel A. Falvo II 2016-10-08 11:27:30 -07:00
  • 9fc0b8848f Ladies and gentlemen, Polaris. Samuel A. Falvo II 2016-10-08 11:23:13 -07:00
  • 5c04466afe WIP V5 CSRRC(I) now works. Samuel A. Falvo II 2016-10-08 08:58:25 -07:00
  • 84d7866a3f WIP V5 CSRRS (works), CSRRC (doesn't), and CSRR?I. Samuel A. Falvo II 2016-10-08 00:20:51 -07:00
  • 412c0b3e71 WIP V5 CSRRWI Samuel A. Falvo II 2016-10-07 23:01:36 -07:00
  • d4fe5f07ee WIP V5 CSRRW. Samuel A. Falvo II 2016-10-07 22:37:49 -07:00
  • 5e88a8123c Add MPIE and MIE bits. Samuel A. Falvo II 2016-10-07 09:04:33 -07:00
  • 1f39095ffe WIP V5 MRET instruction Samuel A. Falvo II 2016-10-06 22:11:44 -07:00
  • ec7038e791 WIP V5 ECALL and EBREAK support. Samuel A. Falvo II 2016-10-03 23:24:59 -07:00
  • 19818c170f WIP V5 FENCE instructions Samuel A. Falvo II 2016-10-02 14:12:17 -07:00
  • e26313b6e7 WIP V5 Conditional branches! Wooo! Samuel A. Falvo II 2016-10-02 13:24:29 -07:00
  • 8ce9cf319d Cleanup; unsure why merge did not remove these Samuel A. Falvo II 2016-10-02 10:56:39 -07:00
  • ffed70aa41 V5 WIP JAL completed Samuel A. Falvo II 2016-10-01 21:08:29 -07:00
  • 0fe687192b cleanup Samuel A. Falvo II 2016-10-01 20:42:37 -07:00
  • 803e597a16 cleanup Samuel A. Falvo II 2016-10-01 20:41:58 -07:00
  • c1e64c7193 New dependencies in Makefile Samuel A. Falvo II 2016-10-01 20:31:37 -07:00
  • 05615ba990 V5 WIP STORE completed. Samuel A. Falvo II 2016-10-01 20:26:48 -07:00
  • d7fd6dcc4d V5 WIP LOAD instructions supported. Samuel A. Falvo II 2016-10-01 19:27:03 -07:00
  • 4570c91ee2 V5 WIP File restructuring. Samuel A. Falvo II 2016-09-30 23:29:09 -07:00
  • 56b999ea61 V5 WIP LUI AUIPC done Samuel A. Falvo II 2016-09-30 23:14:50 -07:00
  • 905c48adcc V5 WIP Implement OP-REG and OP-REG-32 instructions. Samuel A. Falvo II 2016-09-30 21:45:46 -07:00
  • 998bebf502 V5 WIP Remove duplicate tests Samuel A. Falvo II 2016-09-30 20:36:37 -07:00
  • dcfb3b1b85 V5 WIP Why does this fail on MacOS Samuel A. Falvo II 2016-09-30 20:25:09 -07:00
  • 9babc79b2c V5 WIP: Support OP-IMM-32 instruction classes too. Samuel A. Falvo II 2016-09-25 21:53:57 -07:00
  • 6456806963 V5 WIP: ANDI, SLLI confirmed. Samuel A. Falvo II 2016-09-25 21:15:28 -07:00
  • 2a68d0983e V5 WIP: ADDI and JALR finished. Samuel A. Falvo II 2016-09-25 21:00:29 -07:00
  • fc94eaa569 V5 WIP Fix register address bug Samuel A. Falvo II 2016-09-25 11:40:32 -07:00